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Computer Architecture 2011 – PC Structure and Peripherals 1 Computer Architecture PC Structure and Peripherals Dr. Lihu Rappoport.

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Presentation on theme: "Computer Architecture 2011 – PC Structure and Peripherals 1 Computer Architecture PC Structure and Peripherals Dr. Lihu Rappoport."— Presentation transcript:

1 Computer Architecture 2011 – PC Structure and Peripherals 1 Computer Architecture PC Structure and Peripherals Dr. Lihu Rappoport

2 Computer Architecture 2011 – PC Structure and Peripherals 2 DRAM

3 3 Basic DRAM chip u DRAM access sequence  Put Row on addr. bus and assert RAS# (Row Addr. Strobe) to latch Row  Put Column on addr. bus and assert CAS# (Column Addr. Strobe) to latch Col  Get data on address bus Row Address Latch Row Address decoder Column addr decoder CAS# RAS# Data Memory array Addr Column Address Latch

4 Computer Architecture 2011 – PC Structure and Peripherals 4 DRAM Operation u DRAM cell consists of transistor + capacitor  Capacitor keeps the state; Transistor guards access to the state  Reading cell state: raise access line AL and sense DL Capacitor charged  current to flow on the data line DL  Writing cell state: set DL and raise AL to charge/drain capacitor  Charging and draining a capacitor is not instantaneous u Leakage current drains capacitor even when transistor is closed  DRAM cell periodically refreshed every 64ms AL DL C M

5 Computer Architecture 2011 – PC Structure and Peripherals 5 DRAM Access Sequence Timing  Put row address on address bus and assert RAS#  Wait for RAS# to CAS# delay (tRCD) between asserting RAS and CAS  Put column address on address bus and assert CAS#  Wait for CAS latency (CL) between time CAS# asserted and data ready  Row precharge time: time to close current row, and open a new row tRCD – RAS/CAS delay tRP – Row Precharge RAS# Data A[0:7] CAS# Data n Row iCol n Row j X CL – CAS latency X

6 Computer Architecture 2011 – PC Structure and Peripherals 6 DRAM controller u DRAM controller gets address and command  Splits address to Row and Column  Generates DRAM control signals at the proper timing u DRAM data must be periodically refreshed  DRAM controller performs DRAM refresh, using refresh counter DRAM address decoder Time delay gen. address mux RAS# CAS# R/W# A[20:23] A[10:19] A[0:9] Memory address bus D[0:7] Select Chip select

7 Computer Architecture 2011 – PC Structure and Peripherals 7  Paged Mode DRAM – Multiple accesses to different columns from same row – Saves RAS and RAS to CAS delay  Extended Data Output RAM (EDO RAM) – A data output latch enables to parallel next column address with current column data Improved DRAM Schemes RAS# Data A[0:7] CAS# Data nD n+1 RowXCol n XCol n+1 XCol n+2 X D n+2 X RAS# Data A[0:7] CAS# Data nData n+1 RowXCol n XCol n+1 XCol n+2 X Data n+2 X

8 Computer Architecture 2011 – PC Structure and Peripherals 8  Burst DRAM – Generates consecutive column address by itself Improved DRAM Schemes (cont) RAS# Data A[0:7] CAS# Data nData n+1 RowXCol n X Data n+2 X

9 Computer Architecture 2011 – PC Structure and Peripherals 9 Synchronous DRAM – SDRAM u All signals are referenced to an external clock (100MHz-200MHz)  Makes timing more precise with other system devices u 4 banks – multiple pages open simultaneously (one per bank) u Command driven functionality instead of signal driven  ACTIVE: selects both the bank and the row to be activated ACTIVE to a new bank can be issued while accessing current bank  READ/WRITE: select column u Burst oriented read and write accesses  Successive column locations accessed in the given row  Burst length is programmable: 1, 2, 4, 8, and full-page May end full-page burst by BURST TERMINATE to get arbitrary burst length u A user programmable Mode Register  CAS latency, burst length, burst type u Auto pre-charge: may close row at last read/write in burst u Auto refresh: internal counters generate refresh address

10 Computer Architecture 2011 – PC Structure and Peripherals 10 SDRAM Timing u t RCD : ACTIVE to READ/WRITE gap =  t RCD (MIN) / clock period  u t RC : successive ACTIVE to a different row in the same bank u t RRD : successive ACTIVE commands to different banks BL = 1

11 Computer Architecture 2011 – PC Structure and Peripherals 11 DDR-SDRAM u 2n-prefetch architecture  DRAM cells are clocked at the same speed as SDR SDRAM cells  Internal data bus is twice the width of the external data bus  Data capture occurs twice per clock cycle Lower half of the bus sampled at clock rise Upper half of the bus sampled at clock fall u Uses 2.5V (vs. 3.3V in SDRAM)  Reduced power consumption n:2n-1 0:n-1 200MHz clock 0:2n-1 SDRAM Array 400M xfer/sec

12 Computer Architecture 2011 – PC Structure and Peripherals 12 DDR SDRAM Timing 133MHz clock cmd Bank Data Addr NOP X ACT Bank 0 Row iX RD Bank 0 Col j t RCD >20ns ACT Bank 0 Row l t RC >70ns ACT Bank 1 Row m t RRD >20ns CL=2 NOP X X X X X X RD Bank 1 Col n NOP X X X X X X X X j n

13 Computer Architecture 2011 – PC Structure and Peripherals 13 DIMMs u DIMM: Dual In-line Memory Module  A small circuit board that holds memory chips u 64-bit wide data path (72 bit with parity)  Single sided: 9 chips, each with 8 bit data bus  Dual sided: 18 chips, each with 4 bit data bus  Data BW: 64 bits on each rising and falling edge of the clock u Other pins  Address – 14, RAS, CAS, chip select – 4, VDC – 17, Gnd – 18, clock – 4, serial address – 3, …

14 Computer Architecture 2011 – PC Structure and Peripherals 14 DDR Standards u DRAM timing, measured in I/O bus cycles, specifies 3 numbers  CAS Latency – RAS to CAS Delay – RAS Precharge Time u CAS latency (latency to get data in an open page) in nsec  CAS Latency × I/O bus cycle time u Total BW for DDR400  3200M Byte/sec = 64 bit  2  200MHz / 8 (bit/byte)  6400M Byte/sec for dual channel DDR SDRAM Standard name Mem. clock (MHz) I/O bus clock (MHz) Cycle time (ns) Data rate (MT/s) V DDQ (V) Module name transfer rate (MB/s) Timing (CL-tRCD- tRP) CAS Latency (ns) DDR PC DDR ⅓ ⅔ PC ⅓ DDR ⅔ 6333 ⅓ PC ⅔ DDR PC

15 Computer Architecture 2011 – PC Structure and Peripherals 15 DDR2 u DDR2 doubles the bandwidth  4n pre-fetch: internally read/write 4× the amount of data as the external bus  DDR2-533 cell works at the same freq. as a DDR266 cell or a PC133 cell  Prefetching increases latency u Smaller page size: 1KB vs. 2KB  Reduces activation power – ACTIVATE command reads all bits in the page u 8 banks in 1Gb densities and above  Increases random accesses u 1.8V (vs 2.5V) operation voltage  Significantly lower power Memory Cell Array I/O Buffers Data Bus Memory Cell Array I/O Buffers Data Bus Memory Cell Array I/O Buffers Data Bus

16 Computer Architecture 2011 – PC Structure and Peripherals 16 DDR2 Standards Standard name Mem clock (MHz) Cycle time I/O Bus clock (MHz) Data rate (MT/s) Module name Peak transfer rate Timings CAS Latency DDR ns PC MB/s DDR ns PC MB/s DDR ns 333 MHz 667 PC MB/s DDR ns 400 MHz 800 PC MB/s DDR ns 533 MHz 1066 PC MB/s

17 Computer Architecture 2011 – PC Structure and Peripherals 17 DDR3 u 30% power consumption reduction compared to DDR2  1.5V supply voltage, compared to DDR2's 1.8V  90 nanometer fabrication technology u Higher bandwidth  8 bit deep prefetch buffer (vs. 4 bit in DDR2 and 2 bit in DDR) u Transfer data rate  Effective clock rate of 800–1600 MHz using both rising and falling edges of a 400–800 MHz I/O clock  DDR2: 400–800 MHz using a 200–400 MHz I/O clock  DDR: 200–400 MHz based on a 100–200 MHz I/O clock u DDR3 DIMMs  240 pins, the same number as DDR2, and are the same size  Electrically incompatible, and have a different key notch location

18 Computer Architecture 2011 – PC Structure and Peripherals 18 DDR3 Standards Standard Name Mem clock (MHz) I/O bus clock (MHz) I/O bus Cycle time (ns) Data rate (MT/s) Module name Peak transfer rate (MB/s) Timings (CL-tRCD- tRP) CAS Latency (ns) DDR PC ⁄ 2 15 DDR ⅓ 533 ⅓ ⅔ PC ⅓ ⁄ ⁄ 8 15 DDR ⅔ 666 ⅔ ⅓ PC ⅔ ⁄ 2 DDR PC ⁄ ⁄ ⁄ 4 DDR ⅓ 933 ⅓ ⅔ PC ⅓ ⁄ ⁄ 7 DDR ⅔ 1066 ⅔ ⅓ PC ⅔ ⁄ ⁄ 16

19 Computer Architecture 2011 – PC Structure and Peripherals 19 DDR2 vs. DDR3 Performance The high latency of DDR3 SDRAM has negative effect on streaming operations Source: xbitlabsxbitlabs

20 Computer Architecture 2011 – PC Structure and Peripherals 20 SRAM – Static RAM u True random access u High speed, low density, high power u No refresh u Address not multiplexed u DDR SRAM  2 READs or 2 WRITEs per clock  Common or Separate I/O  DDRII: 200MHz to 333MHz Operation; Density: 18/36/72Mb+ u QDR SRAM  Two separate DDR ports: one read and one write  One DDR address bus: alternating between the read address and the write address  QDRII: 250MHz to 333MHz Operation; Density: 18/36/72Mb+

21 Computer Architecture 2011 – PC Structure and Peripherals 21 SRAM vs. DRAM u Random Access: access time is the same for all locations DRAM – Dynamic RAMSRAM – Static RAM RefreshRefresh neededNo refresh needed AddressAddress muxed: row+ columnAddress not multiplexed AccessNot true “Random Access”True “Random Access” densityHigh (1 Transistor/bit)Low (6 Transistor/bit) Powerlowhigh Speedslowfast Price/bitlowhigh Typical usageMain memorycache

22 Computer Architecture 2011 – PC Structure and Peripherals 22 Read Only Memory (ROM) u Random Access u Non volatile u ROM Types  PROM – Programmable ROM Burnt once using special equipment  EPROM – Erasable PROM Can be erased by exposure to UV, and then reprogrammed  E 2 PROM – Electrically Erasable PROM Can be erased and reprogrammed on board Write time (programming) much longer than RAM Limited number of writes (thousands)

23 Computer Architecture 2011 – PC Structure and Peripherals 23 Hard Disks

24 Computer Architecture 2011 – PC Structure and Peripherals 24 Hard Disk Structure u Rotating platters coated with a magnetic surface  Each platter is divided to tracks: concentric circles  Each track is divided to sectors Smallest unit that can be read or written  Disk outer tracks have more space for sectors than the inner tracks Constant bit density: record more sectors on the outer tracks speed varies with track location u Moveable read/write head  Radial movement to access all tracks  Platter rotation to access all sectors u Buffer Cache  A temporary data storage area used to enhance drive performance Platters Track Sector

25 Computer Architecture 2011 – PC Structure and Peripherals 25 Hard Disk Structure

26 Computer Architecture 2011 – PC Structure and Peripherals 26 Disk Access u Seek: position the head over the proper track  Average: Sum of the time for all possible seek / total # of possible seeks  Due to locality of disk reference, actual average seek is shorter: 4 to 12 ms u Rotational latency: wait for desired sector to rotate under head  The faster the drives spins, the shorter the rotational latency time  Most disks rotate at 5,400 to 15,000 RPM At 7200 RPM: 8 ms per revolution  An average latency to the desired information is halfway around the disk At 7200 RPM: 4 ms u Transfer block: read/write the data  Transfer time is a function of: sector size, rotation speed, and recording density: bits per inch on a track  Typical values: 100 MB / sec u Disk Access Time = Seek time + Rotational Latency + Transfer time + Controller Time + Queuing Delay

27 Computer Architecture 2011 – PC Structure and Peripherals 27 EIDE Disk Interface u EIDE, PATA, UltraATA, ATA 100, ATAPI: all the same interface  Uses for connecting hard disk drives and CD/DVD drives  80-pin cable, 40-pin dual header connector  100 MB/s  EIDE controller integrated with the motherboard u EIDE controller has two channels  Primary and a secondary, which work independently  Two devices per channel: master and slave, but equal The 2 devices take turns in controlling the bus  If there are two device on the system (e.g., a hard disk and a CD/DVD) It is better to put them on different channels  Avoid mixing slower (DVD) and faster devices (HDD) on the same channel  If doing a lot of copying from drive to drive Better performance by separating devices to separate channels

28 Computer Architecture 2011 – PC Structure and Peripherals 28 Disk Interface – Serial ATA (SATA) u Point-to-point connection  Dedicated BW per device (no sharing)  No master/slave jumper configuration needed when a adding a 2 nd SATA drive u Increased BW  SATA rev 1: 150 MB/sec  SATA rev 2: 300 MB/sec  SATA rev 3: 600 MB/sec u Thinner (7 wires), flexible, longer cables  Easier routing, easier installation, better reliability, improved airflow  1/6 the board area compared to EIDE connector  4 wires for signaling + 3 ground to minimize impedance and crosstalk u Current HDDs still do not utilize SATA rev 3 BW  HDD peak (not sustained) gets to 157 MB/s  SSD gets to 250 MB/sec

29 Computer Architecture 2011 – PC Structure and Peripherals 29 Flash Memory u Flash is a non-volatile, rewritable memory u NOR Flash  Supports per-byte data read and write (random access) Erasing (setting all the bits) done only at block granularity (64-128KB) Writing (clearing a bit) can be done at byte granularity  Suitable for storing code (e.g. BIOS, cell phone firmware) u NAND Flash  Supports page-mode read and write (0.5KB – 4KB per page) Erasing (setting all the bits) done only at block granularity (64-128KB)  Suitable for storing large data (e.g. pictures, songs) Similar to other secondary data storage devices  Reduced erase and write times  Greater storage density and lower cost per bit

30 Computer Architecture 2011 – PC Structure and Peripherals 30 Flash Memory Principles of Operation u Information is stored in an array of memory cells  In single-level cell (SLC) devices, each cell stores one bit  Multi-level cell (MLC) devices store multiple bits per cell using multiple levels of electrical charge u Each memory cell is made from a floating-gate transistor  Resembles a standard MOSFET, with two gates instead of one A control gate (CG), as in other MOS transistors, placed on top A floating gate (FG), interposed between the CG and the MOSFET channel  The FG is insulated all around by an oxide layer  electrons placed on it are trapped Under normal conditions, will not discharge for many years  When the FG holds a charge, it partially cancels the electric field from the CG Modifies the cell’s threshold voltage (V T ): more voltage has to be applied to the CG to make the channel conduct  Read-out: apply a voltage intermediate between the possible threshold voltages to the CG Test the channel's conductivity by sensing the current flow through the channel In a MLC device, sense the amount of current flow

31 Computer Architecture 2011 – PC Structure and Peripherals 31 Flash Write Endurance u Typical number of write cycles u Bad block management (BBM)  Performed by the device driver software, or by a HW controller E.g., SD cards include a HW controller perform BBM and wear leveling  Map logical block to physical block Mapping tables stored in dedicated flash blocks or Each block checked at power-up to create a bad block map in RAM  Each write is verified, and block is remapped in case of write failure  Memory capacity gradually shrinks as more blocks are marked as bad u ECC compensates for bits that spontaneously fail  22 (24) bits of ECC code correct a one bit error in 2048 (4096) data bits  If ECC cannot correct the error during read, it may still detect the error SLCMLC NAND flash100K1K – 3K NOR flash100K to 1M100K

32 Computer Architecture 2011 – PC Structure and Peripherals 32 Flash Write Endurance (cont) u Wear-leveling algorithms  Evenly distribute data across flash memory and move data around  Prevent from one portion to wear out faster than another  SSD's controller keeps a record of where data is set down on the drive as it is relocated from one portion to another u Dynamic wear leveling  Map Logical Block Addresses (LBAs) to physical Flash memory addresses  Each time a block of data is written, it is written to a new location Link the new block Mark original physical block as invalid data Blocks that never get written remain in the same location u Static wear leveling  Periodically move blocks which are not written  Allow these low usage cells be used by other data

33 Computer Architecture 2011 – PC Structure and Peripherals 33 Solid State Drive – SSD u Most manufacturers use "burst rate" for Performance numbers  Not its steady state or average read rate u Any write operation requires an erase followed by the write  When SSD is new, NAND flash memory is pre-erased u Consumer-grade multi-level cell (MLC)  Allows ≥2 bit per flash memory cell  Sustains 2,000 to 10,000 write cycles  Notably less expensive than SLC drives u Enterprise-class single-level cell (SLC)  Allows 1 bit per flash memory cell  Lasts 10× write cycles of an MLC u The more write/erase cycle  the shorter the drive's lifespan  Use wear-leveling algorithms to evenly distribute writes  DRAM cache to buffer data writes to reduce number of write/erase cycles  Extra memory cells to be used when blocks of flash memory wear out

34 Computer Architecture 2011 – PC Structure and Peripherals 34 SSD (cont.) u Data in NAND flash memory organized in fixed size in blocks  When any portion of the data on the drive is changed Mark block for deletion in preparation for the new data Read current data on the block Redistribute the old data Lay down the new data in the old block  Old data is rewritten back  Typical write amplification is 15 to 20 For every 1MB of data written to the drive, 15MB to 20MBs of space is actually needed Using write combining reduces write amplification to ~10% u Flash drives compared to HD drives:  Smaller size, faster, lighter, noiseless, lower power  Withstanding shocks up to 2000 Gs (like 10 foot drop onto concrete)  More expensive (cost/byte): ~2$/1GB vs ~0.1$/1GB in HDD

35 Computer Architecture 2011 – PC Structure and Peripherals 35 The Motherboard

36 Computer Architecture 2011 – PC Structure and Peripherals 36 Computer System Structure – 2009 Core PCI North Bridge (GMCH) DDRII Channel 1 mouse LAN Lan Adap External Graphics Card Mem BUS LLC Sound Card speakers South Bridge (ICH) PCI express ×16 IDE controller IO Controller Old DVD Drive Hard Disk Parallel Port Serial Port Floppy Drive keybrd DDRII Channel 2 USB controller SATA controller PCI express ×1 Memory controller On-board Graphics CPU BUS Core HDMI

37 Computer Architecture 2011 – PC Structure and Peripherals 37 Computer System – Nehalem PCI North Bridge mouse LAN Lan Adap External Graphics Card CPU BUS Sound Card speakers South Bridge PCI express ×16 SATA controller IO Controller DVD Drive Hard Disk Parallel Port Serial Port Floppy Drive keybrd USB controller SATA controller PCI express ×1 On-board Graphics Cache DDRIII Channel 1 Mem BUS DDRIII Channel 2 Memory controller Core HDMI

38 Computer Architecture 2011 – PC Structure and Peripherals 38 Computer System – Westmere PCI North Bridge mouse LAN Lan Adap External Graphics Card Sound Card speakers South Bridge (PCH) PCI express ×16 SATA controller IO Controller DVD Drive Hard Disk Parallel Port Serial Port Floppy Drive keybrd USB controller SATA controller PCI express ×1 On-board Graphics Cache DDRIII Channel 1 Mem BUS DDRIII Channel 2 Memory controller Core HDMI MCP – Multi Chip Package Display link

39 Computer Architecture 2011 – PC Structure and Peripherals 39 Computer System – Sandy Bridge mouse LAN Lan Adap South Bridge (PCH) Audio Codec DVD Drive Hard Disk Parallel Port Serial Port Floppy Drive PS/2 keybrd/ mouse Cache DDRIII Channel 1 Mem BUS DDRIII Channel 2 Memory controller Core D-sub, HDMI, DVI, Display port External Graphics Card PCI express ×16 GFX Display link MHz Line in Line out S/PDIF in S/PDIF out Super I/O LPC USB SATA BIOS PCI express ×1 exp slots System Agent 4×DMI

40 Computer Architecture 2011 – PC Structure and Peripherals 40 PCH Connections u LPC (Low Pin Count) Bus  Supports legacy, low BW I/O devices  Typically integrated in a Super I/O chip Serial and parallel ports, keyboard, mouse, floppy disk controller  Other: Trusted Platform Module (TPM), Boot ROM u Direct Media Interface (DMI)  The link between an Intel north bridge and an Intel south bridge Replaces the Hub Interface  DMI shares many characteristics with PCI-E Using multiple lanes and differential signaling to form a point-to-point link  Most implementations use a ×4 link, providing 10Gb/s in each direction DMI 2.0 (introduced in 2011) doubles the BW to 20Gb/s with a ×4 link u Flexible Display Interface (FDI)  Connects the Intel HD Graphics integrated GPU with the PCH south bridge where display connectors are attached  Supports 2 independent 4-bit fixed frequency links/channels/pipes at 2.7GT/s data rate

41 Computer Architecture 2011 – PC Structure and Peripherals 41 Motherboard Layout – 1 st Gen Core2 TM IEEE- 1394a header audio header PCI add-in card connector PCI express x1 connector PCI express x16 connector Back panel connectors Processor core power connector Rear chassis fan header LGA775 processor socket GMCH: North Bridge + integ GFX Processor fan header DIMM Channel A sockets Serial port header DIMM Channel B sockets Diskette drive connector Main Power connector Battery ICH: South Bridge + integ Audio 4 × SATA connectors Front panel USB header Speaker Parallel ATA IDE connector High Def. Audio header PCI add-in card connector

42 Computer Architecture 2011 – PC Structure and Peripherals 42 Motherboard Layout (Sandy Bridge) IEEE- 1394a header audio header PCI add-in card connector PCI express x1 connector PCI express x16 connector Back panel connectors Processor core power connector Rear chassis fan header LGA775 processor socket Processor fan header DIMM Channel A sockets Serial port header DIMM Channel B sockets Main Power connector Battery PCH SATA connectors Front panel USB headers Bios setup config jumper High Def. Audio header S/PDIF speaker Front chassis fan header Chassis intrusion header Rear chassis fan header

43 Computer Architecture 2011 – PC Structure and Peripherals 43 ASUS Sabertooth P67 B3 Sandy Bridge Motherboard

44 Computer Architecture 2011 – PC Structure and Peripherals 44 How to get the most of Memory ? u Single Channel DDR u Dual channel DDR  Each DIMM pair must be the same u Balance FSB and memory bandwidth  800MHz FSB provides 800MHz × 64bit / 8 = 6.4 G Byte/sec  Dual Channel DDR400 SDRAM also provides 6.4 G Byte/sec CH A DDR DIMM DDR DIMM CH B L2 Cache CPU FSB – Front Side Bus DRAM Ctrlr L2 Cache CPU FSB – Front Side Bus Memory Bus DRAM Ctrlr DDR DIMM

45 Computer Architecture 2011 – PC Structure and Peripherals 45 How to get the most of Memory ? u Each DIMM supports 4 open pages simultaneously  The more open pages, the more random access  It is better to have more DIMMs n DIMMs: 4n open pages u DIMMs can be single sided or dual sided  Dual sided DIMMs may have separate CS of each side In this case the number of open pages is doubled (goes up to 8) This is not a must – dual sided DIMMs may also have a common CS for both sides, in which case, there are only 4 open pages, as with single side

46 Computer Architecture 2011 – PC Structure and Peripherals 46 Motherboard Back Panel USB 2.0 ports LAN port USB 2.0 ports USB 3.0 ports eSATA USB 2.0 ports DisplayPortHDMI DVI-I IEEE 1394A Rear Surround Line in Line out/ Front speakers S/PDIF Center / subwoofer Mic in / Side surround

47 Computer Architecture 2011 – PC Structure and Peripherals 47 System Start-up Upon computer turn-on several events occur: 1. The CPU "wakes up" and sends a message to activate the BIOS 2. BIOS runs the Power On Self Test (POST): make sure system devices are working ok  Initialize system hardware and chipset registers  Initialize power management  Test RAM  Enable the keyboard  Test serial and parallel ports  Initialize floppy disk drives and hard disk drive controllers  Displays system summary information

48 Computer Architecture 2011 – PC Structure and Peripherals 48 System Start-up (cont.) 3. During POST, the BIOS compares the system configuration data obtained from POST with the system information stored on a memory chip located on the MB  A CMOS chip, which is updated whenever new system components are added  Contains the latest information about system components 4. After the POST tasks are completed  the BIOS looks for the boot program responsible for loading the operating system  Usually, the BIOS looks on the floppy disk drive A: followed by drive C: 5. After boot program is loaded into memory  It loads the system configuration information contained in the registry in a Windows® environment, and device drivers 6. Finally, the operating system is loaded

49 Computer Architecture 2011 – PC Structure and Peripherals 49 Backup

50 Computer Architecture 2011 – PC Structure and Peripherals 50 Western Digital HDDs Caviar Green 2TBCaviar Blue 1TBCaviar Black 2TB Maximum external transfer rate 300MB/s Maximum sustained data rate126MB/s138MB/s Average rotational latency4.2 ms Spindle speed7,200 RPM Cache size32MB64MB Platter size500GB Areal density400 Gb/in² Available capacities2TB Idle power6.1W8.2W Read/write power6.8W10.7W Idle acoustics28 dBA29 dBA Seek acoustics33dBA30-34 dBA

51 Computer Architecture 2011 – PC Structure and Peripherals 51 HDD Example Performance Specifications Rotational Speed 7,200 RPM (nominal) Buffer Size 64 MB Average Latency 4.20 ms (nominal) Load/unload Cycles 300,000 minimum Transfer Rates Buffer To Host (Serial ATA) 6 Gb/s (Max) Physical Specifications Formatted Capacity 2,000,398 MB Capacity 2 TB Interface SATA 6 Gb/s User Sectors Per Drive 3,907,029,168 Acoustics Idle Mode 29 dBA (average) Seek Mode 0 34 dBA (average) Seek Mode 3 30 dBA (average) Current Requirements Power Dissipation Read/Write Watts Idle 8.20 Watts Standby 1.30 Watts Sleep 1.30 Watts

52 Computer Architecture 2011 – PC Structure and Peripherals 52 DDR Comparison DDR SDRAM Standard Bus clock (MHz) Internal rate (MHz) Prefetch (min burst) Transfer Rate (MT/s) Voltage DIMM DIMM pins DDR 100–200 2n 200– DDR2 200– –2664n400– DDR3400– –2668n800–

53 Computer Architecture 2011 – PC Structure and Peripherals 53 SSD vs HDD Attribute or characteristicSolid-state driveHard disk drive Random accessRandom access time [57] [57] ~0.1 ms5–10 ms Consistent read performance [61] [61] Read performance does not change based on where data is stored on an SSD If data is written in a fragmented way, reading back the data will have varying response times FragmentationNon-issue due Files may fragment; periodical defragmentation is required to maintain ultimate performance. AcousticAcoustic levelsSSDs have no moving parts and make no sound Mechanical reliabilityNo moving part Maintenance of temperatureLess heat Susceptibility to environmental factorsenvironmental factors No flying heads or rotating platters to fail as a result of shock, altitude, or vibrationshock MagneticMagneticsusceptibilityNo impact on flash memoryMagnets or magnetic surges can alter data on the media Weight and sizevery light compared to HDDs Parallel operation Some flash controllers can have multiple flash chips reading and writing different data simultaneously HDDs have multiple heads (one per platter) but they are connected, and share one positioning motor. Write longevity Flash-based SSDs have a limited number of writes (1-5 million or more) over the life of the drive. Magnetic media do not have a similar limited number of writes but are susceptible to eventual mechanical failure. Cost per capacity$.90–2.00 per GB$0.05/GB for 3.5 in and $0.10/GB for 2.5 in drives Storage capacityTypically 4-256GBtypically up to 1 – 2 TB Read/write performance symmetry Less expensive SSDs typically have write speeds significantly lower than their read speeds. Higher performing SSDs have a balanced read and write speed. HDDs generally have slightly lower write speeds than their read speeds. Free block availability and TRIMTRIM SSD write performance is significantly impacted by the availability of free, programmable blocks. Previously written data blocks that are no longer in use can be reclaimed by TRIM; however, even with TRIM, fewer free, programmable blocks translates into reduced performance. [29][75][76] [29][75][76] HDDs are not affected by free blocks or the operation (or lack) of the TRIM command Power consumption High performance flash-based SSDs generally require 1/2 to 1/3 the power of HDDs High performance HDDs require watts; drives designed for notebook computers are typically 2 watts.

54 Computer Architecture 2011 – PC Structure and Peripherals 54 PC Connections Name Raw bandwidth (Mbit/s) Transfer speed (MB/s) Max. cable length (m) Power provided Devices per channel eSATA 3, with eSATA HBA (1 with passive adapter)HBA No 1 (15 with port multiplier)port multiplier eSATAp5 V/12 V [33] [33] SATA revision 3.06, [34] [34] 1No SATA revision 2.03, SATA revision 1.01, [35] [35] 1 per line PATAPATA 1331, (18 in)No2 SAS 6006, No 1 (>65k with expanders) SAS 3003, SAS 1501, IEEE 1394IEEE , (more with special cables) 15 W, 12–25 V63 (with hub) IEEE 1394IEEE [36] [36] IEEE 1394IEEE [36][37] [36][37] USBUSB 3.0*5, [38] [38] 3 [39] [39] 4.5 W, 5 V 127 (with hub) [39] [39] USBUSB [40] [40] 2.5 W, 5 V USBUSB Yes SCSISCSI Ultra-6405, No15 (plus the HBA) SCSISCSI Ultra-3202, Fibre Channel Fibre Channel over optic fibre 10,5201,0002–50,000 No 126 (16,777,216 with switches) Fibre Channel Fibre Channel over copper cable 4, InfiniBand InfiniBand Quad Rate 10,0001,000 5 (copper) [41][42] <10,0 00 (fiber) [41][42] No 1 with point to point Many withswitched fabricpoint to pointswitched fabric Thunderbolt10,0001, W7


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