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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 1 Training Electrical Engineers on Asynchronous Logic Circuits Based on Constant Weight Codes P. Keresztes, L.T Kóczy, A.Nagy, G. Rózsa Department of Automation, Széchenyi István University, H-9026 Győr Egyetem tér 1. HUNGARY keresztp@sze.hu, koczy@sze.hu, anagy@sze.hu, rozsa@sze.hu keresztp@sze.hukoczy@sze.huanagy@sze.hu rozsa@sze.hu

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 2 CONTENTS ● Széchenyi István University, Győr, Hungary ● Main branches of Eletrical Engineering in University of Győr ● Courses connecting to digital design ● The problem of clocking in SoC complexity VLSI, and solutions ● Delay insensitive asynchronous circuits ● Different approaches in teaching of DI asynchronous systems ● Detailes of our mixed TD/BU training method

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 3 Győr, a university city in Hungary

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 4 Széchenyi István University in Győr

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 5 Preliminary and/or related courses in Electrical Engineering BSc level : Digital Networks Digital Signal Processing ASIC design Application of microcontrollers MSc level :Digital systems Microprocessor architectures CMOS circuit design

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 6 Main chapters of the course ‘Digital Networks’ ●Minimization of switching functions and combinational networks ●Design process of synchronous sequential networks ●Design process of Huffmann-type asynchronous sequential networks ●Introduction to register-transfer level ●Introduction to microprocessor architectures

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 7 Main Chapters of Course ‘Digital Systems’ ● Introduction to VHDL and its application ● VHDL modeling and simulation in the design process of synchronous and Huffmann-type asynchronous sequential networks ● The delay insensitive asynchronous networks, their VHDL modeling and simulation ● High level synthesis of unisynchronous, multisynchronous and delay-insensitive asynchronous systems.

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 8 Possible approaches to build up a discipline for DI asynchronous systems ● Hystorical approach ● Bottom-up approach ● Top-down approach ● A combination of top-down and bottom-up approaches

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 9 The problem of ‘clocking’ in high complexity VLSI Delay of long interconnections can be much larger then the gate-delay, i.e. - delay of long interconnections limits the clock frequeccy, or - delay of long interconnections makes wrong the synchronous operation

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 10 Solutions for ‘clocking problem’ The system consists of smaller synchronous units, which communicate asynchronously (Locally synchronous, globally asynchronous systems) Application of Delay Locked Loop (DLL) circuits Application of asynchronous units which communicate asynchronously (Locally and globally asynchronous systems, DI systems)

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 11 Three basic concepts of delay insensitive systems ● Dennis static DATA-FLOW graphs (1991) ● 4 phase asynchronous communication in multisynchronous systems ● Application of constant weight ( m-of-n) binary codes for implementation of tokens (valid versus invalid data)

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 12 Two models of DENNIS- static dataflow actor Firing: The ACTOR fires, if there are data with tokens on all inputs, and the output is free from token.

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 13 A REFINED DENNIS ACTOR

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 14 4-phase handshake communication in a multisynchronous system

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 15 D.E. Müller and his famous circuit ‘C’

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 16 Rules for valid-invalid and invalid-valid transitions Among the transient states which appear during the transitions neither the invalid state nor any of the valid states may appear. PROPOSAL : Constant weight codes

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 17 Substitution of signal ‘request’ by ‘validity’ in Dual-Rail DI circuits ● ‘request is high’ is substituted by validity of data. ● ‘request is low’ is substituted by invalidity of data. For example : DUAL-RAIL circuits X1 X0X LLN LH‘0’ HL‘1’ Valid data Invalid data

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 18 A possible ‘2-of-5’ BCD code completed with code-word ‘NULL’

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 19 Invalid-valid transitions on constant weight code variables ‘1-of-2’ : L L L H, L L H L ‘2-of-3’ 0 0 0 0 0 1 0 1 1, 0 0 0 0 1 0 0 1 1 ‘2-of-5’ : 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 ‘3-of-6’ : 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 20 Simple actor ‘INCREMENTER’ (A DSCH scheme)

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 21 Let’s simulate the actor ‘INCREMENTER’ with DSCH system!

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 22 A student task: Let’s make an abstract level VHDL description for a two input DI incrementer Three communicating processes have to be in the architecture Process 1: process(x, ack_strd_x, strd_x1) (asynchronous register for x) Process 2: process(i, ack_strd_i, strd_i) (asynchronous register for i) Process 3: process(strd_x, strd_i, y) (A combinational network with logic completeness and hysteresis)

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 23 Hardware implementations of the processes Process 1: process(x, ack_strd_x, strd_x1) Detect the completion of x, Sample x and hold it on otput strd_x1 until ack_strd_x rises Process 2: process(i, ack_strd_i, strd_i) Detect the completion of DR variable i, Sample i and hold it until ack_strd_i rises Process 3 : process(strd_x, strd_i, y) Detect the completion of strd_x and strd_i Place the value of INCR on output y, Detect the invalidity of both strd_x and strd_i Place the NULL on output y.

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 24 Now the Müller-C can be analized

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 25 This is the point of the course, when the direction is changed to BOTTOM-UP

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 26 COMPONENTS OF DI-ACTORS ● DI-registers ● DI-combinational networks

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 27 Properties of DI-registers ● Transparency during the transient when the input goes from invalid to valid ● Acknowledgement of valid data for the driver (Completion detector) ● Holding valid data until the receiving acknowledgement from all driven registers and the end of input transient from valid to invalid.

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 28 DI-register (‘2-of-5’ code)

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 29 VHDL behavioural model of DI registers process(d, ack_y, y) begin if ack_y = ’0’ then y <= d after td; if d /= NULL and d /= TRANS then ack_d <= ’1’ after td; end if; elsif y /= NULL and y /= TRANS and ack_y = ’1’ and d = NULL then y <= TRANS after td, NULL after td; ack_d <= ’0’ after td + td; end if; end process;

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 30 Logic completeness and hysteresis with hysteresis decoders Logic completeness is demanded (all inputs have to be valid) before the output goes invalid to valid and (all inputs have to be invalid) before output goes valid to invalid.

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 31 DI-COMBNETS : DR XOR

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 32 VHDL behavioural model of DI- COMBNETS process ( x1, x2, y) begin if x1 /= NULL and x1 /= TRANS and x2 /= NULL and X2 /= TRANS and y = NULL then y <= TRANS after td, FUNC(x1, x2) after td + td; elsif x1 = NULL and x2 = NULL and y /= NULL and y /= TRANS then y <= TRANS after td, NULL after td + td; end if; end process;

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 33 Scheme of the ACTOR ‘INCR’

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 34 Let’s simulate ACTOR ‘INCR’ with DSCH simulation system

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 35 CONCLUSIONS The new approach detailed above not only allows students a more in-depth understanding of the basic principles of the operation of delay-insensitive logic circuits, but also enables them to select the optimal constant-weight codes for the particular case.

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 36 Thanks for your attention

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P. Keresztes, L.T. Kóczy, A. Nagy, G.Rózsa: Training Electrical Engineers on Asynchronous Logic Circuits on Constant Weight Codes 37 Rules of firing TD-DF actors in implemented systems The actor senses one of the input transitions from invalid to valid. It stores the value of the valid datum, and it informs of this fact the driving actor by the placement of a token on the acknowledge output belonging to the valid input. If all the inputs have got from invalid to valid state, and they have been acknowledged, the actor checks upon the state of its output. If it is invalid, the actor transfers a valid datum to the output, whose value corresponds to its function. If in this situation, any of the driving actors changes the driven input of the actor to invalid, the actor will delete the token, if, and only if all the actors driven by it have acknowledged the receipt. The actor renders its output invalid, if, and only if all the inputs have become invalid, and all driven actors have acknowledged the receipt.

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