Presentation is loading. Please wait.

Presentation is loading. Please wait.

Q3’13 ArxCis-NV TM NVDIMM Technology & Roadmap Review.

Similar presentations


Presentation on theme: "Q3’13 ArxCis-NV TM NVDIMM Technology & Roadmap Review."— Presentation transcript:

1 Q3’13 ArxCis-NV TM NVDIMM Technology & Roadmap Review

2 2 NEW MEMORY LANDSCAPE SCM (STORAGE CLASS MEMORIES) ARGUABLY NOT VIABLE FOR MAINSTREAM ADOPTION FOR ~ 4-5 YRS NVDIMM

3 3 NVDIMM is “leading the charge” of Non-Volatility & Persistence to main memory Will lead to radical changes in computing / storage architecture / paradigms Many different usage models, with strong Value Prop Arxcis-NV Technical Overview

4 4 FEATURES Arxcis-NV Technical Overview »DRAM Capacities: 2GB, 4GB, 8GB »DDR3 1.5V 1333MT/s »NAND 2x DRAM Capacity »Multiple Host Trigger Methods (incl ADR) »Supercapacitor Charged via DIMM »Save / ~10 sec/GB Powered by SuperCapacitors in event of power-failure DRAM Endurance & Speed NAND for Persistence

5 5 Fastest storage tier, 11GB/S, DDR3 DIMM speed & bandwidth more than 300% faster than PCI-E (3.2GB/S). 1.4 million IOPS Read & Write, 3 times faster than PCI-E cards. (430K Write IOPS) DRAM chips never wear out, no limit on number of writes. DIMM interface “talks” to CPU more directly. 1000x better latency performance than PCI-E, 10 nanoseconds vs 10 microseconds. Complete solution with supercap, monitors supercap health. ArxCis NVDIMM Key Features I. Arxcis-NV Technical Overview

6 6

7 7

8 8

9 9

10 10 Use as RAMDISK, and data will be saved in event of power failure. (PRAMDISK) Faster recover from power failure, back to system environment before power failure. Support Instant On, apps layer data kept in flash, fastest boot. Configure as block device for caching, performance + endurance. Memcache application pushing up demand for NVDIMM. Support both ADR & NMI power failure data saving functions. Intel’s chosen partner for NVDIMM enablement for Grantely platform. ArxCis NVDIMM Key Features II. Arxcis-NV Technical Overview

11 11 -Removing need to write on SSDs, extend life of SSD based servers. -No need over-provisioning, releasing extra storage space from SSDs. -No operation cycles wasted on wear leveling. -No longer a “write cliff”, nor need to closely monitor drive usage. -Rapid increase in ROI for enterprise or data center applications. ArxCis NVDIMM, Perfect Match For SSD based Enterprise & DCN Systems. Arxcis-NV Technical Overview

12 12 ArxCis NVDIMM Actual Installation. Arxcis-NV Technical Overview

13 13 ArxCis NVDIMM Actual Installation. Arxcis-NV Technical Overview

14 14 ARXCIS-NV TM NVDIMM – HOW IT FUNCTIONS Arxcis-NV Technical Overview

15 15 Arxcis-NV Technical Overview NVDIMM: HOW IT FUNCTIONS (SAVE) SuperCap powers Sub-system P/FAIL System Crash DATA SAVE FROM DRAM TO FLASH

16 16 Arxcis-NV Technical Overview NVDIMM: HOW IT FUNCTIONS (RESTORE) SuperCap powers Sub-system P/FAIL System Crash RESTORES DATA FROM FLASH TO DRAM Host can access RESTORED data

17 17 ARXCIS-NV BLOCK DIAGRAM Arxcis-NV Technical Overview

18 18 ARXCIS-NV OPERATING MODE Arxcis-NV Technical Overview

19 19 ARXCIS-NV TM ROADMAP Arxcis-NV Technical Overview

20 20 NVDIMM (DDR INTERFACE) Arxcis-NV Technical Overview Product2H ‘131H ‘142H ‘141H ‘15 DDR3 RDIMM DDR3 LRDIMM DDR4 RDIMM Committed

21 21 ARXCIS-NV TM DDR4 FEATURES Arxcis-NV Technical Overview

22 22 DDR4 DRAM Interface. DDR4 JEDEC pin-out. Module 1.2V. 1866MT/s Min Speed for ES. 2133MT/ for QS. 2DPC) Data Transfer Speeds (DRAM   Max 5 sec/GB. OEM target of <60sec for SAVE/RESTORE of 16GB DIMM. NVDIMM meets JEDEC Standard DDR4 (X-Y-Z) Mechanical dimensions (note DDR4 module max height increases to 31.25mm) 1-Rank & 2-Rank Module Configurations Required. 2 nd rank enabled via DDP/BGA stacking – Supporting 36 physical DRAM packages on DIMM 4Gb Mono DRAM Base: 8GB 1-Rank & 16GB 2-Rank 8Gb Mono DRAM Base: 16GB 1-Rank & 32GB 2-Rank SSD capacity – (Appropriately sized for contents of DRAM + ECC) Encryption AES-256 & Password Lock Multiple Image support DDR4 FEATURE SUPPORT Arxcis-NV Technical Overview

23 23 Early warning detection of Flash/SSD failure / wear-out, Bad block count / detection. Erase operation. Host can initiate an erase operation to securely delete data on SSD. In-field Firmware upgradable. Firmware Reliability Feature. In case of firmware hang, watch dog timer feature implemented in FPGA to reset itself JEDEC Pin-227 SAVE-pin Intel MRC support 12V pins. Design NVDIMM to support host systems using 12V pin as route of power (i.e consolidated supercap pack) Build option to support supercap tethered individually to the DIMM. DDR4 FEATURE SUPPORT (MISC) Arxcis-NV Technical Overview

24 24 NVDIMM SYSTEM INTEGRATION VIKING NVDIMM SUPPORTS BOTH “ADR” & “NMI” TRIGGER - SANDY BRIDGE - IVY BRIDGE Arxcis-NV Technical Overview

25 25 »Early Power Failure Hardware NMI Signal To Processor »SAVE_n Signal Routed From Processor To NVDIMM »Power Supply w/ minimum 1 msec holdup post power loss »NVDIMM-Aware System BIOS »NMI Handler And Driver NMI TRIGGER SYSTEM SUPPORT REQUIREMENTS (ALTERNATE TO ADR) Arxcis-NV Technical Overview

26 26 » ArxCis-NV™ Is A Storage Device. » The Same Techniques Used To Enhance Data Integrity With Traditional Storage Devices Can Be Applied To ArxCis-NV » DIMM Mirroring  Built into Sandybridge memory controller » Memory Scrubbing » Intel Machine Check Architecture  Provides ability to handle some memory related faults that would have crashed system in earlier architectures » Software Techniques  Software RAID  Checkpointing / Journaling SYSTEM LEVEL RELIABILITY ENHANCEMENT Arxcis-NV Technical Overview

27 27 ITEMDescription ArxCis-NV Datasheet [1]NVDIMM datasheet providing AC and DC electrical characteristics, detailed functional description, status/command register definitions, and module pinout. ArxCis-NV System Hardware Design Guide [2]Provides guidance on required motherboard hardware support and power supply selection. ArxCis-NV Event Handler Specification [3]Describes function and implementation of ArxCis-NV Linux NMI Handler. ArxCis-NV Event Handler Reference CodeLinux open source reference code written in C. ArxCis-NV NVDriver Specification [4]Describes function and implementation of ArxCis-NV driver, which is required to map ArxCis into application memory space. ArxCis-NV NVDriver Reference CodeLinux open source reference code written in C. ArxCis-NV Management Driver Specification [5]Describes function and implementation of ArxCis-NV management driver, which serves as an interface for applications to access ArxCis-NV management interfaces, such as supercapacitor health monitoring info. ArxCis-NV Management Driver Reference CodeLinux open source reference code written in C. ArxCis-NV BIOS Porting Guide [6]Describes required BIOS modifications for ArxCis-NV support. Code base is AMI BIOS distribution for Intel Rose City platform (Sandybridge). ArxCis-NV BIOS Reference CodeC code distributed to customer at no cost under terms of Viking’s license with AMI. ArxCis-NV EFI POST Test Specification [7]Describes Power on self test module for ArxCis-NV. ArxCis-NV EFI POST Test Reference Code.Reference code written in C for the ArxCis-NV POST test module. SUPPORT DOCUMENTATION AND REFERENCE CODE Arxcis-NV Technical Overview

28 28 SUPERCAP PACKS FOR INTERNAL HDD BRACKET ArxCis-NV Supercapacitor packs Designed to be retained in internal 2.5” HDD bracket ArxCis-NV Supercap options 1.2GB NVDIMM 2.4GB NVDIMM 3.8GB NVDIMM Upper row of 3 = 8GB Pack Lower row of 2 = 4GB Pack Lower row of 1 = 2GB Pack (not shown) Viking Confidential

29 29 SUPERCAPACITOR BLADES Cylindrical Supercapacitor power source to fit 1.2 width chassis. Viking Product Portfolio

30 30 GLOBAL LOCATIONS European Headquarters Lerchenstrasse 1 D Gunzenhausen Germany Phone: Japan Headquarters Shinagawa Grand Central Tower Konan, Minato-Ku Phone: Singapore Headquarters No 2 Chai Chee Drive Singapore, Phone: U.S. Headquarters Ellipse Foothill Ranch, CA Phone: Fax: Arxcis-NV Technical Overview


Download ppt "Q3’13 ArxCis-NV TM NVDIMM Technology & Roadmap Review."

Similar presentations


Ads by Google