3 OutlineSyllabus highlightsGood lab procedures for ECE 201Hardware used in labECE 209 lab kitNI-ELVIS –IISoftware used in the labDigital WorksSafety video
4 Syllabus Highlights Grade Composition: Grading Scale: A: 90-100% 25 % Pre-lab preparation and design25% Class performance and demonstration of functional circuits30% Full lab reports20% Final project and presentationGrading Scale:A: %B: 75-89%C: 60-74%D: 50-59%F: <50%
5 Syllabus Highlights (cont.) Pre-lab Preparation and Design (25% of grade):Thoroughly read the experiment in the manual before coming to the lab.Pre-lab reports are to be turned in before each lab and may consist of simulation(s), diagrams, truth tables, K-maps, etc.Wiring you circuits prior to coming to lab will make the lab quicker and easier for both the student and instructor. Pre-wiring circuits will also reduce the chance of students not having enough time to complete the lab.
6 Syllabus Highlights (cont.) Class Performance/Functional Circuits (25% of grade):Attend each lab and participateCorrectly wire the circuits required in the lab manual and demonstrate that the circuit functions correctly to the instructorAttendance is mandatory for every lab; however, if the instructor is not in the classroom within 15 minutes after the class is scheduled to start, then the students are free to leave (unless they have been told otherwise in advance).
7 Syllabus Highlights (cont.) Full Lab Reports (30% of grade):Throughout the semester there will be 3 full lab reports assigned, each will count as 10% of your overall grade. These reports must be typed using a word processor. Grades will be based on organization, content, neatness, accuracy, conclusions, and format. A standard format is as follows (format may vary with different instructors):Title Page (Title, date, due date, author, lab partner(s))Objectives (Succinctly state the purpose of the lab)Procedure (State what you did (circuit diagrams) and present results)ConclusionCollege of Engineering Honor Code and Signature
8 Syllabus Highlights (cont.) Final Project and Presentation (20% of grade):There is NOT A FINAL EXAM for this lab course. Instead there will be a project involving design, simulation, and analysis of a digital-circuit related to a concept of your choice.You may work individually or in groups of 2One report will be required for each groupYour group will give a presentation about your project during the last lab sessionYou will receive more information regarding this project in the second half of the semester.
9 Good lab proceduresBe very careful while wiring circuitsDon’t leave wire dangling aboutMake sure all the connections are made correctly (reverse power leads can destroy your IC chips)Before wiring always draw a circuit diagram with pin numbers and chips labeledWhile wiring and rewiring turn off the powerAvoid messy wiringHandle equipment carefullyBefore leaving lab check to make sure your bench position is neat and orderly
10 Hardware – ECE 209 Lab KitProtoboard:Inserting IC chips on a protoboard
11 Hardware – ECE 209 Lab Kit (cont.) Integrated Circuits (ICs):IC pin numbers: The position of pin 1 is determined by a dot or notch on the IC. The numbers typically increase in the counterclockwise direction (but there are exceptions). Once we know the pin numbers, we can use the chip pin-out to create our circuit.NotchActual ChipChip Pin-out Diagram
12 Hardware – ECE 209 Lab Kit (cont.) Each IC chip has a number stamped on it, identifying what type of logic chip it is. For example the chip below is a 7486 logic chip which contains 4, 2-input XOR gates. Once we know the IC number, we can find the chip pin-out in pages in the lab manual.
13 Hardware – ECE 209 Lab Kit (cont.) IC Handling:Before using the ICs we must first straighten out the legs by gently flattening the IC on a table top as shown below. Be careful, the legs/pins are very fragile.
14 Hardware – ECE 209 Lab Kit (cont.) Removing ICs:Ideally we would use an IC extractor, but we will usually just use a pencil to gently remove ICs from the protoboard. First loosen the IC on one end, and then loosen as shown below. This is to prevent the legs/pins from bending.Loosen One End of the ICLoosen Second End and Remove
15 Examples of Basic Gates – AND gate An AND gate can be depicted by 2 switches in seriesRef:
16 Examples of Basic Gates – OR gate An OR gate can be depicted by 2 switches in parallelRef:
17 Hardware – NI ELVIS II1: On-Off switch2: PWR SEL Jumper3: Power Supply4: Logic Inputs5: Lamp Monitors (LEDs)6: Function Generator7: Analog Inputs
18 Hardware – NI ELVIS II (cont.) Powering the Circuits:For our circuits to operate the NI-ELVIS board must be turned on (there are two switches which need to be “on”, the one pictured in the previous diagram and one on the back right side of the board).The ICs in our circuits will require Vcc (+5 V) and GND (ground) according to the pin-outs. The pins for Vcc and GND are in the “Power Supply” area of the board; area 3 in the previous slide.
19 Hardware – NI ELVIS II (cont.) Digital Inputs:Most, if not all of our circuits will require digital inputs. i.e. inputs that are either logic 1 (+5 V) or logic 0 (GND). We could manually move a wire between the +5 V and GND pins, but it is easier to use a specialized pin that we can change between +5 V and GND with software.The specialized pins that we will use as digital inputs to our circuits are shown in area 4 of the NI-ELVIS diagram (DI0 – DI7).
20 Hardware – NI ELVIS II (cont.) Controlling Digital Inputs:Open the “NI ELVISmx Instrument Launcher” on the computer and the following GUI will appear.Select “DigOut” and the GUI to the right will appear.Hit the “Run” buttonClick the oval corresponding to the desired input to toggle it between +5 V and GNDDI0=oval 0, DI1=oval 1, etc.“Ovals”
21 Software – Digital Works Simulations using Digital Works:There is a link on the lab homepage (for 32 bit machines) as well as a link in the syllabus (for 64 bit machines) where you can download Digital Works (DW).Using DW we can simulate circuits and determine if they are functioning how they should before actually building a circuit on our protoboard. Labeling chips and pin numbers in the simulation will also make it much easier to wire circuits in the lab.For a basic introduction to using DW go the the “Digital Works Introduction” link on the lab homepage.
22 Software – Digital Works (cont.) Basic Logic GatesInteractive InputLED (output)Annotation(labeling)Wiring ToolRun buttonObject Interaction
23 Software – Digital Works (cont.) The following is an example of simulating a OR gate in Digital Works Z = X + Y
24 Contact InformationInstructor:Name:Office:Phone:Office Hours: As needed ( for appointment)Lab Coordinator:Name: Dr. Timothy BurgOffice: 307 Fluor Daniel (EIB)Phone: (864)
26 Laboratory 1 – Logic gates: A smart lighting system
27 Introduction to Laboratory 1 Objective: Explore notion of combinational circuits and basic combinational designRequirementsDigital works simulation for all 3 circuitsVerbal description of the function of final circuitTruth table for first function (the light controller)
28 Lab overviewDesign a circuit that controls a light with 5 inputThe light is turned on whenBurglar Alarm (B) detects an intruderMaster Light Switch (M) is onAn Auxiliary Switching system (A1, A2) is on and a Person (P) is present in the room (person detector is on)
29 Logic equation: XOR function for auxiliary switching system: : Person detected AND auxiliary switching system on: Master Switch is on OR Person is detected AND Auxiliary switching system is onDesired lighting function is
31 Implementing a Function with different gates Implement the XOR function using only AND and OR gatesSimulate the circuit in digital worksWiring the circuit is optional.
32 Realizing an Arbitrary Boolean Function Design a circuit using only truth tables and logic functionLogic function isSimulate and wire the circuit using AND, OR and NOT gates
33 Preparations for Next Week Next week’s lab Encoding/Decoding: The Seven-Segment DisplayRequirements:Simulation of functional seven-segment display circuitTruth table for all seven segments and all seven functions in MSOP
34 Laboratory 2 – Encoding/Decoding: The Seven-segment display
35 Introduction to Laboratory 2 Objective: Become familiar with the seven-segment LED display, encoding/decoding, and BCD (binary coded decimal)Requirements:Simulation of functional seven-segment display circuitTruth table for all seven segments and all seven functions in MSOP
36 Decoding/Encoding Decoding: Encoding: Decoding is the conversion of a n-bit input code to a m-bit output code with n ≤ m ≤ 2n. As an example, the inputs (Ai) and the outputs (Di) for a 2-to-4 line decoder are shown below:Encoding:Encoding is the inverse operation of decoding. An encoder converts a m-bit input to a n-bit output with n ≤ m ≤ 2n. The above table would represent an encoder if the D’s were inputs and the A’s were outputs.M. M. Mano and C. R. Kime, Logic and Computer Design Fundamentals
37 Binary Coded Decimal (BCD) When converting from decimal to BCD we convert each decimal digit individually using the following table:A decimal number in BCD is the same as its equivalent binary number only when the number is between 0 and 9 (inclusive). A BCD number greater than 10 has a representation different from its equivalent binary number. This can be seen below for the conversion of decimal 185:(185)10 = ( )BCD = ( )2185M. M. Mano and C. R. Kime, Logic and Computer Design Fundamentals
38 Seven-Segment Display Decimal numbers are displayed by a seven-segment display as shown in the figureThe truth table and logic function for segment A are
39 Seven-Segment Display (cont.) There are two types of seven segment displaysCommon Anode (what we have)Common connection tied to +5vLogic low inputs used to light LEDCommon CathodeCommon connections tied to groundLogic high input lights up LED220 Ω resisters critical to limit current through LEDs
40 7447 BCD to Seven-Segment Display A truth table can be made for all of the segments, but because this function is very common, a single chip has been standardized to perform this conversion. The chip is the 7447.The chip can be connected as follows
41 Preparation for next week Next week’s lab - Combinational Circuits: Parity Generation and DetectionRequirementsK-map for parity generator and detectorTruth table for parity detectorSimulation of functional parity generator/detector
42 Laboratory 3 – Combinational Circuits: Parity generation and detection
43 Introduction to Laboratory 3 Objective: Familiarize students with combination circuitsRequirementsK-map for parity generator and detectorTruth table for parity detectorSimulation of functional parity generator/detector
44 Combinational Circuit Circuit implemented using Boolean circuitsUses gates exclusively, so that it deals with boolean functionsCannot store memory – Has no provision to store past inputs and outputsUsed for doing boolean algebra in computer circuits
45 Karnaugh MapBecomes difficult to implement larger boolean expressions -More expressions -> More gates -> Complex circuit -> Difficult to connect and implementExpressions can be reduced mathematically, but a tough nut to crackKarnaugh Maps makes expression as simple as possible, as well as its solving processUseful for combinational circuit – reduces the boolean expression substantially
47 Parity GeneratorUsed to detect whether the number of 1s in the input is even or odd, indicated by a parity bitUsed for detecting errors in the received dataTwo types:Even parity – Parity bit -> high, when 1s -> odd. Makes total number of 1s even in the setOdd Parity – Parity bit -> high, when 1s ->even. Makes total number of 1s odd in the set
48 Parity Generator contd… By your knowledge so far, along with new information, what do you think is the basic parity generator? And what type?How parity bits are used (Even Parity):1PARITY BITPARITY BITPARITY BIT
49 Parity generator contd… For an odd parity generator with three inputs and one output, the truth table isXYZP1
51 Parity Generator contd… P = X’Y’Z’ + XY’Z + X’YZ +XYZ’P = [X’(Y’Z’+YZ)] + [X(Y’Z + YZ’)]P = [X’ AND (Y⊕Z)’] + [X AND (Y⊕Z)]Original Number of 2-input gates(4 x NOT) + (6 x AND) + (4 x OR) =14 gatesNumber of 2-input Gates for the highlighted expression(2 x NOT) + (1 x XOR) + (2 x AND) + (1 x OR) =6 gates
52 Parity Generator contd… 6 Gates sound too much still, isn’t it?Let’s check the highlighted equation again:P = [X’ AND (Y⊕Z)’] + [X AND (Y⊕Z)]Let (Y⊕Z) = WP = [X’ AND W’] + [X AND W]P = X’W’ + XWWhat does this remind you of?P = X XNOR W=> P = (X ⊕ W)’Replacing the value of WP = (X ⊕ Y ⊕ Z)’Number of 2-input gates now => (2 x XOR) + (1 x NOT)=> 3 gates!
54 Parity detectorNo use of parity generators, if there’s nothing to acknowledge – or check for – the parity bitsChances exist of noise in data sent over a communication channelErrors detected using parity detectorsParity generator and detector go hand-in-hand
55 Parity detector contd… Odd parity detector for 3 inputs
56 Parity detector contd… K-Map for Odd parity detectorZ’P’Z’PZPZP’X’Y’X’YXYXY’
57 Parity detector contd… E = (X ⊕ Y ⊕ Z ⊕ P )’ Number of 2-input Gates for the highlighted expression (3 x XOR) + (1 x NOT) = 4 gates
58 Parity generator and detector Create parity generator and detector circuits and connect them as shown in the figure belowAlso simulate a communication where a single bit error is introduced to any of the four inputs to parity detector
59 Lab ReportDue Next LabObjective – Goal of the labSplit the report into two parts hereJust mention the parts, and start from the same page. No need for separate pages to indicate separate parts.
60 Lab Report contd…Part 1: Parity GeneratorSchematic Diagram – One will sufficeExplanationWhat is a Parity Generator?Truth TableK-MapDerive the equation that you used in the labImportanceResult – Explain your result as you understood
61 Lab Report contd…Part 2: Parity DetectorSchematic Diagram – One will suffice. You can show “P” as an input. No need to attach parity generator circuit to it.ExplanationWhat is a Parity Detector?Truth TableK-MapDerive the equation that you used in the labImportanceResult – Explain your result as you understood
62 Lab Report contd…Conclusions – Write the conclusion based on your experience while working with K-maps, gates, and parity-generator and –detector.Honor Code – Limit to one important paragraph
63 Preparation for next week Read about binary arithmetic and propertiesLearn more about K-maps, and how they are used to reduced the number of elements in the expressionUnderstand binary half-adders and full-adders, and difference between themGenerate truth tables for half- and full-addersThough half-adder is not mentioned in the lab-manual, we’ll be doing it the next class
65 Introduction to Laboratory 4 Objective: Demonstrate knowledge of simple binary arithmetic and mechanics of its useRequirementsSimulation of functional Full Adder
66 Half AdderWhen 2 single bits A and B are added the truth table and K-maps for this operation are as follows:Sum (S)Carry (C)BB1A1AFrom the truth table and or K-maps we can determine that the functions for C and S are as shown below.
67 Half Adder (cont.)Now consider the addition of two 8-bit binary numbers:We can see that we are actually adding three bits, two bits from the numbers being added and one additional carry bit.Since the half adder does not take this carry bit (Cin) into consideration a new model is needed. This new model is a full adder.
68 Full AdderThe truth table and K-maps for the full adder are shown below.Sum (S)Carry Out (Cout)ABABCin000111101Cin000111101The familiar checkerboard pattern in S and the circled groups in Cout lead to the full adder functions that are shown below.
69 Full Adder (cont.)A circuit diagram which creates the sum (S) and carry (Cout) bits of a full adder is shown below.
70 Building 2-bit Full Adder Two full adders can be combined to make a 2-bit adder as shown in the diagram belowBuild a 2-bit adder on your bread-board and test the circuit
71 Preparation for next week Next week’s lab: MSI Circuits – Four-Bit Adder/Subtractor with Decimal OutputRequirementsSimulation of functional circuit
73 Introduction to Laboratory 5 Objective: Familiarize students with MSI technology, specifically adders and also 1’s complement arithmeticRequirementsSimulation of functional Full Adder
74 Representation of Negative Numbers as Binary Ideally, a binary number is represented in an “exponential of 2” number of bits, i.e. 2, 4, 8, 16 …Three types of negative-number representation. Interested only in 1’s complement, i.e. complementing of every bit of the original number to get negative counterpartE.g.4- bit 1’s Complement 8-bit 1’s complement7 –-7 – –Why is it known as 1’s complement?Because it is obtained by subtracting the unsigned number from 0’s complement. Try it yourself.
75 4-Bit Adder & Subtractor The 7483 chip is a 4 bit full adderSubtraction is addition of a positive and a negative numberApart from addition, the chip can be used for 1’s complement subtraction
76 Example of 1’s complement subtraction Take 1’s complement of 1 i.e. (-1)Add (-1) to 7Add the carry bit to the resultResult of addition is the final resultRef: Wikipedia
77 Building 1’s Complement Subtractor Take 1’s complement using XOR gates to complement a bit when input is 1Why not NOT gate?Input to determine the nature of adder0: Addition1:Subtraction
78 Steps for 1’s compliment subtraction If the numbers are in decimal-form, convert them to binaryTake 1’s complement of the subrahend.Add the 1’s complement to minuendInstead of keeping carry bit as the extended form of difference, add it to the answerS4 S3 S2 S1 is the final answer for add/subtract
82 Lab Report – Due Next Lab Objective – Goal of the labEquipment usedSplit the report into two parts hereJust mention the parts, and start from the same page. No need for separate pages to indicate separate parts.
83 Lab Report (cont.)Part 1: 1-bit Full AdderSchematic Diagram – DigitalWorksExplanationWhat is a Full Adder?Truth TableK-MapMention the equation that you used in the lab
84 Lab Report (cont.) Part 2: 4-bit Subtractor Schematic Diagram - DigitalWorksExplanationConcept of 1’s complement subtractionA short statement on MSI chip and the one used hereExplanation for circuit used, including the usage of gates, resistors, BCD-to-decimal converter, and LED displayTruth table for LED display and BCD-to-decimal converter
85 Lab Report (cont.)Result – Answer the questions mentioned in the lab manualConclusions – Write the conclusion based on your experience while working with K-maps, gates, and parity-generator and –detector.Honor Code – Limit to one important paragraph
86 Preparation for next week Next week’s lab : Multiplexers and Serial CommunicationRequirementsSimulation of functional circuit
87 Laboratory 6 – Multiplexers and serial communication
88 Introduction to Laboratory 6 Objective: Familiarize students with internal realization of multiplexers and show an application of multiplexers and demultiplexers in serial communicationsRequirementsSimulation of functional circuit
89 MultiplexerA multiplexer is a combinational circuit that selects binary information from 2n input lines and directs the information to a single output line by using n select linesThe lab manual gives the analogy of a rotary switch like in the above figure. This is an accurate comparison but note that there is not an actual switch in the multiplexers.The input line that is connected to the output line is determined by the select lines (S0 and S1) and logic gates.
91 Why do we need multiplexers? Multiplexer (cont.)Why do we need multiplexers?Less Power Consumption in DisplaysThe lab manual gives the example of multiplexing the seven-segment displays of a calculator to reduce power usage and therefore increase battery lifeWhat about LED advertisement boards being viewed in slow motion?Communication SystemsWhen there are several independent inputs which need to travel over the same line.Consider the arrangement of phone lines.
92 DemultiplexerA demultiplexer is another type of combinational circuit.The function of a demultiplexer is opposite to the function of a multiplexer.The demultiplexer takes a single input line and sends it to one of 2n output lines depending on the value of the n select lines.
93 Demultiplexer (cont.)Since we do not have a 1-to-8 demultiplexer, we will have to create one from the chip. The contains two 1-to-4 demultiplexers.To do this, make the following connections:Connect “Strobe GA” and “Strobe GB” together Input lineConnect “Data CA” and “Data CB” together 3rd select lineNote: The notation for the figures in the lab manual does not match exactly with the pinouts for the chips!
94 Application of multiplexer/demultiplexer Connect the following circuit to multiplex the segments of the seven-segment display with a serial communication line.Connect “clock” of the to the function generator of the NI ELVIS board. Use a square waveform with a Vpp of 3 volts.
95 Preparation for next week Next week’s lab : Four – Bit Combinational MultiplierRequirementsSimulation of functional circuit
97 Introduction to Laboratory 7 Objective: Practice the combinational design process through the design of a 4-bit multiplierRequirementsSimulation of functional circuitNo wiring necessary for this lab
98 4 bit multiplicationExample of a 4 bit multiplicationThe individual multiplication can be obtained by the AND operation and 4-bit adder can be used for addition
99 Complete multiplication Sij represents the jth output of the ith adderS05 , S16 and S7 are carry from the 4 bit adderOnly 4 bit adders are needed for addition as P00, S01 and S12 are directly given to the output
100 Preparation for next week Next week’s lab : Logic Design for a Direct-Mapped CacheRequirementsSimulation of functional circuit along with all the macros used
101 Laboratory 8 – Logic design for a direct-mapped cache
102 Introduction to Laboratory 8 Objective: Understand the function and design of a direct-mapped cacheRequirementsSimulation of functional circuit along with all the macros usedNo wiring necessary for this lab
103 Terminology 1 Byte = 8 bits (i.e. 1001 0110 is one byte) 1 kilobyte (kB) = 210 bytes = 1,024 bytes(as opposed to the equality: 1 kilometer = 103 meters = 1,000 meters)1 megabyte (MB) = 220 bytes = 1,048,576 bytes(as opposed to the equality: 1 megameter = 106 meters = 1,000,000 meters)1 gigabyte (GB) = 230 bytes = 1,073,741,824 bytes(as opposed to the equality: 1 gigameter = 109 meters = 1,000,000,000 meters)
104 Basic Computer Organization BackgroundThe CPU requires data from memory (instructions for programs and numerical data)When a computer needs to read from memory it generates a memory addressThe next step is to locate where the data associated with the address is currently residingThe first memory it checks is the cache, if it is there it is a cache hit, otherwise it is a missBasic Computer OrganizationA. S. Tanenbaum, Structured Computer Organization
105 Moving Down the Pyramid Background (cont.)few ns (10-9 s)/~100 bytesfew ns (10-9 s)/few megabytestens of ns (10-9 s)/thousands of megabytestens of ms (10-3 s)/few gigabytesseveral seconds/limited only by budget (kept separate)Moving Down the PyramidLonger access times (slower)Increased storage capacity (larger)Cost per bit decreases (cheaper)Data most frequently needed is kept in small, fast, but expensive memory.Less frequently needed data is kept in large, slow, and cheap memory.A. S. Tanenbaum, Structured Computer Organization
106 Direct-mapped cacheThe goal of this lab will be to develop logic which determines whether or not the required data is in the cache (the output will indicate whether we have a cache hit or a miss).Our fictional computer is characterized by the following:16 bit address bus 216 = 210*26 = 1 kB*64 = 64 kB (total memory)16 line cache with 256 bytes each 256 B*16 = 28*24 = 210*22 = 1 kB*4 = 4 kB (data from memory that can be stored in the cache)Line2,byte1Line2,byte2Line2,byte3Line2,byte4Line2,byte256Line3,byte1Line3,byte2Line3,byte3Line3,byte4Line3,byte256Line4,byte1Line4,byte2Line4,byte3Line4,byte4Line4,byte256Line1,byte1Line1,byte2Line1,byte3Line1,byte4Line1,byte256...Line16,byte1Line16,byte2Line16,byte3Line16,byte4Line16,byte256.Cache Structure
107 Direct-mapped cache (cont.) The 16 bit memory address is arranged as shownCache line address indicates which line in the cache the address will be inTag tells us which block is present(Offset)
108 ExampleOnly memory addresses whose cache line address field matches can be in a particular cache (only one block per cache line).One block
109 Lab Procedure We will not be concerned with the “offset” bits. We will be working with the “tag” bits of the address which are stored in a tag memory that is associated with the cache.We will also be working with a “valid” bit in the tag memory which indicates if the information in the cache is valid.
110 Lab Procedure (cont.)Based on the information in the previous slides, we will need a 16x5 tag memory. We will implement the tag memory in Digital Works using ROM (initialized according to the table to the right).Inputs to the ROM will be the “cache line address bits” and the “tag” bits of the memory address (i.e. you will need 8 inputs in your simulation).The “cache line address” bits will determine which line in the cache to retrieve the tag from. The retrieved tag bits will then be compared with the tag bits in the memory address.Use a comparator to turn on an LED if the retrieved tag bits are the same as the tag bits in the memory address and the valid bit is a one.
111 The XNOR function can be used to compare 2 bits Note on comparatorsThe XNOR function can be used to compare 2 bitsTwo 4-bit binary numbers are the same if and only if the two 1st bits are equivalent and the two 2nd bits are equivalent and the two 3rd bits are equivalent and the two 4th bits are equivalent
112 Preparation for next week Next week’s lab : Understand the design and restrictions of Sequential CircuitsRequirementsSimulation of functional circuit
113 Laboratory 9 – Sequential design – three bit counter
114 Introduction to Laboratory 9 Objective: Understand the design and restrictions of Sequential CircuitsRequirementsElectronic copy of your design.Schematic of final design.State Transition Tables.Karnaugh Maps with Boolean reductions for each variable.
115 Sequential CircuitSome circuits need the knowledge of present – as well as past – inputs, along with the outputs it had generated last time.Combinational circuit can’t be used, as it uses only present inputs, and thus has no memorySequential circuit comes in handy in such situationsThe output state of a "sequential logic circuit" depends on:Present Input;Past input; andPast outputIn general, combinational circuit is a type of sequential circuitApplications:Timers, counters, memory-management, etc.Vital for building larger and more complex electronic circuits, such as robots, computers, and digital watches.
116 Flip-flopsFlip-flop is the basic form of a sequential circuitIt uses outputs derived from previous inputs to determine the output from the current inputsTypes of flip-flops:J-K FlipflopS-R FlipflopD FlipflopT Flipflop
117 Three-bit counterCounter – Basic form of sequential circuitStarts counting from 0-higher number – or higher-number-0 – once signal is given to the circuitRequires 4 flipflops to get 3-bit counting (will use D flipflop for this lab)Inputs: c (c = 0 =>up-count; c=1 =>down-count)Inputs from previous operations: Q1, Q2, Q3Outputs: Q1, Q2, and Q3
118 c=0 means count up, c=1 means count down D1 can be easily implemented Logic equations for 3 inputs to D flip flopc=0 means count up, c=1 means count downD1 can be easily implementedD2 can be realized using just 2 XOR gatesFactor out c and c’ to obtain a simple form
119 Implementing D3 using JK flip flop Simplifying D3Comparing equation of D3 with the logic equation of a JK flip flop gives the input to the JK flip flop