4CPU must do the following things : Fetch instruction--- Read instruction from memoryInterpret instruction--- The instruction is decodedFetch data--- Read data from memory or an I/O moduleProcess data--- Perform arithmetic or logical operationWrite data--- Write data to memory or an I/O module
7Register Organization Carlos garrido & jorge montenegro
8Registers CPU must have some working space (temporary storage) Called registersNumber and function vary between processor designsOne of the major design decisionsTop level of memory arrangement
9User Visible Registers General PurposeDataAddressCondition Codes
10How Many GP Registers? Between 8 - 32 Fewer = more memory references More does not reduce memory references and takes up processor real estateSee also RISCOne cycle execution timePipeliningLarge number of registers
11How big? Large enough to hold full address Large enough to hold full wordOften possible to combine two data registersC programmingdouble int a;long int a;
12Condition Code Registers ADVANTAGES:Because condition codes are set by normal arithmetic and data movement instructionsConditional instructions, such as BRANCH are simplified relative to composite instructions, such as TEST AND BRANCH.Condition codes facilitate multi-way branches. For example, a TEST instruction can be followed by two branches, one on less than or equal to zero and one on greater than zero.
13Condition Code Registers DISADVANTAGES:Condition codes add complexity, both to the hardware and software. Condition code bits are often modified in different ways by different instructions.Condition codes are irregular, they are typically not part of the main data path, so they require extra hardware connections.Often condition code machines must add special non-condition-code instructions for special situations anyway.In a pipelined implementation, condition codes require special synchronization to avoid conflicts.
14Control and status registers Program Counter (PC): Contains the address of an instruction to be fetched.Instruction Decoding Register (IR): Contains the instruction most recently fetched.Memory Address Register (MAR): Contains the address of a location in memoryMemory Buffer Register (MBR): Contains a word of data to be written to memory or the most recently read.
15Program status word (PSW) Sign: Contains the sign bit of the result of the last arithmetic operation.Zero: Set when the register is “0”Carry: Set if an operation resulted in a carry addition or subtraction of a higher order bitEqual: Set if a logical compare result is equality.Overflow: Used to indicated arithmetic overflow.Interrupt enable/disable: Used to enable or disable interrupts.
16Supervisor ModeSupervisor: Indicates whether the processor is executing in supervisor mode or user modePrivilege instructionAddress spaceMemory managementProtection domain or Protection RingRingKernel
19Section 12.3 Instruction Cycle An instruction cycle (sometimes called fetch-and- execute cycle, fetch-decode- execute cycle, or FDX) is the basic operation cycle of a computer.It is the process by which a computer retrieves a program instruction from its memory, determines what actions the instruction requires, and carries out those actions.This cycle is repeated continuously by the central processing unit (CPU), from bootup to when the computer is shut down.
20The circuits used in the CPU during the cycle are: Program Counter (PC) –Memory Address Register (MAR) -Memory Data Register (MDR) -Instruction register (IR) –Control Unit (CU) -Arithmetic logic unit (ALU) -There are typically four stages of an instruction cycle that the CPU carries out:Fetch the instruction from memory.2) "Decode" the instruction.3) "Read the effective address" from memory if the instruction has an indirect address.4) "Execute" the instruction.
21Fetch Indirect Cycle Interrupt Execute The instruction cycle is the time in which a single instruction is fetched from memory, decoded, and executed. THE FOUR SUB-CYCLES:FetchReads the next instruction from memory into the processor.Indirect CycleMay require memory access to fetch operands, therefore more memory accesses.InterruptSave current instruction and service the interrupt.ExecuteInterpret the opcode and perform the indicated operation.
22There are six fundamental phases of the instruction cycle: 1.) fetch instruction (aka pre-fetch)2.) decode instruction3.) evaluate address (address generation)4.) fetch operands (read memory data)5.) execute (ALU access)6.) store result (writeback memory data)
23DECODE EVALUATE AND FETCH Decoding the instruction?The decoder interprets what?What is being fetched from memory?What decision is made next?Based on the decision what are the options?What if decision is a direct memory operation?What if decision is an indirect memory operation?
25Instruction Cycle with and without Indirect Cycle…
26Sample question:Given that the instruction cycle is the time in which a single instruction is fetched from memory, decoded, and executed: A microprocessor provides an instruction capable of moving a string of bytes from one area of memory to another. The fetching and initial decoding of the instruction takes 10 clock cycles.Thereafter, it takes 15 clock cycles to transfer each byte.The microprocessor is clocked at a rate of 10 GHz. Determine the length of the instruction cycle for the case of a string of 64 bytes. ANSWER: The length of a clock cycle is 0.1 ns. The length of the instruction cycle for this case is [10 + (15 × 64)] × 0.1 = 960 ns.
27Another example: total number of cycles required To execute the SAL instruction: add A, B, C 1.) Fetch instruction (add) from memory address PC. 2.) Increment PC to address of next instruction. 3.) Decode the instruction and operands. 4.) Load the operands B and C from memory. 5.) Execute the add operation. 6.) Store the result into memory location A. Execution Time Suppose each memory access (fetch, load, store) requires 10 clock cycles and that the PC update, instruction decode, and execution each require 1 clock cycle. The total number of cycles to execute the add instruction is: = 43 cycles/instruction. A CPU running at 100 Mhz (100,000,000 cycles/sec) can execute add instructions at a rate of 100,000,000/43 = 2,325,581 instructions/sec, or ~2.3 Mips (million instructions/sec).
31Data Flow: Execute Cycle The execute cycle:Takes many formsthe form depends on which of the various machine instructions is in the IR.This cycle may involvetransferring data among registersread or write from memoryI/Oinvocation of the ALU
33Instruction Pipelining By separating an instruction cycle into stages, multiple instructions at different stages can be worked on at the same time. For example, Stage 2 of the current instruction can be overlapped with Stage 1 of the next instruction.
34A Two-Stage PipelineAn instruction cycle can be divided into two stages:Fetch: get an op-code from main memory and put it in a registerExecute: decode an op-code and execute the instructionThe execute stage of the current instruction would overlap with the fetch stage of the next instruction.Assuming that fetch and execute use the same number of clock cycles, this would double the speed (in reality, execute takes longer).
36A Six-Stage PipelineFetch instruction (FI): get op-code from memory and put it in a registerDecode instruction (DI): decode op-code and determine addressing modeCalculate operand (CO): get effective address of source operandsFetch operands (FO): get operands from memory and put them in registersExecute instruction (EI): execute instruction and write result to a registerWrite operand (WO): store the result in memoryThis pipeline is more typical of modern computers, especially RISC computers (e.g. MIPS, SPARC, and DLX).Each stage occupies about the same number of clock cycles.
38Why not a 100-Stage Pipeline? If 1 instruction per cycle can be achieved with a 5-stage pipeline, adding more stages would only increase the number registers without increasing speed (it might actually make the computer less efficient). Overlapping of instructions requires additional logic to account for dependencies between instructions (i.e. a memory read after a memory write to the same location).
39Pipeline HazardsResource hazards: when two instructions in the pipeline need to use the same resourceData hazards: when two instructions must be executed in sequence (i.e. a memory write followed by a memory read)Branch hazards: when a conditional branch occurs and the pipeline fetches the wrong instructions
40Resource HazardsA resource hazard occurs when two stages in the pipeline need to use the same resource at the same time. For example, two stages need to read from main memory (assuming that the data hasn’t been cached) when an operand fetch is overlapped with an instruction fetch. In this case, the two stages must be executed in series rather than in parallel, and a delay must be introduced in the pipeline.
43Data HazardsA data hazard occurs whenever data is fetched from a location before it contains the correct value. The “correct” value is whatever value it would contain if the instructions were executed in sequence. Whenever the fetch stage must access data that hasn’t yet been written, the pipeline must be delayed at the fetch stage.
46Pipeline Implementation A pipeline is implemented as a series of sequential circuits, with each stage taking its input from the output of the previous stage
47DEALING WITH BRANCHESThe most difficult part in designing an instruction pipeline is assuring a steady flow of instructions to the initial stages of the pipeline. Several approaches have been taken for dealing with conditional branches.Multiple streamsPrefetch branch targetLoop bufferBranch predictionDelayed branch.
49Multiple streamsA pipeline has disadvantages for a branch instruction because it must choose one of two instructions to fetch the next instruction and may take the wrong choice. One way of dealing with this is to allow the pipeline to fetch both instructions, making use of both streams.With multiple pipelines there are delays for accessing register and memory.Additional branch instructions may enter the pipeline before the original branch decision is resolved.
50Prefetch branch target The target of the branch is prefetched when a conditional branch is recognized in addition to the instruction following the branch. The target is saved until execution, if a branch is taken that means that it has already been prefetched.
51Loop bufferA loop buffer is high speed memory that works in sequence with the instruction fetch stage of the pipeline and it contains the most recently fetched instruction.Instructions fetched in sequence will be available without the usual memory access time.If a branch occurs to be ahead of the address of the branch instruction, the target will already be in the buffer.If the loop buffer is large enough to contain all the instruction in the loop , then the instructions will only have to be fetched once.
56Delayed branchIt’s possible to improve the performance of a pipeline be rearranging instructions within a program, so that the instructions occurs later than actually desired. This branch will not take effect until after the execution of the following instruction.
57Intel PipeliningThe Intel implements a five stage pipeline.FetchDecode stage 1Decode stage 2ExecuteWrite back
59Questions 1 What’s the function of internal processing bus? 2 What’s the similarity between the internal structure as a whole and the internal structure of the CPU?3. What is an instruction cycle?4. What are the four sub cycles of an instruction cycle?5. Is the fetch or execute cycle the same for all CPU?6. What is the sequence of an interrupt cycle?7. How does pipelining increase processor speed?8. What are some pipeline hazards?9. Which computers use a 5-stage pipeline?10. What are the five ways to deal with conditional branches?11. What happens in the fetch cycle inside an Intel 80486?
60ReferencesComputer Organization and Architecture, Designing for Performance, 8/E, Stallings, William Embedded System Design: A Unified Hardware/Software Approach, Vahid, Frank, and Givargis, Tony Wikipedia, “Instruction Cycle” CIS-77 Introduction to Computer Systems