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– 1 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 Sample-and-Hold (S/H) Basics.

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Presentation on theme: "– 1 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 Sample-and-Hold (S/H) Basics."— Presentation transcript:

1 – 1 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 Sample-and-Hold (S/H) Basics

2 ZOH vs. Track-and-Hold (T/H) – 2 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 Zero acquisition time Infinite bandwidth Not realistic T/2 acquisition time Finite bandwidth Practical

3 A Simple T/H (Top-Plate Sampling) – 3 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 MOS technology is naturally suitable for implementing T/H The lowpass SC network determines the tracking bandwidth Non-idealities: signal-dependent R on, charge injection, aperture, etc.

4 Tracking Bandwidth (TBW) – 4 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 Tracking bandwidth determines how promptly V o can follow V i Typically TBW is many times greater than the max signal bandwidth What’s wrong with the concept of “linear filtering” if R on is constant?

5 Dispersion – 5 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 Magnitude response Non-uniform phase delay Non-uniform group delay

6 Dispersion – 6 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 Waveform is not very sensitive to the lowpass magnitude response as long as the signal bandwidth is on the order of TBW Waveform distortion is mainly due to non-uniform phase and group delays

7 Signal-Dependent R on – 7 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 Signal-dependent R on → signal-dependent TBW → extra waveform distortion Neither signal-dependent R on nor dispersion is of concern if TBW is sufficiently large (>> f in, depending on the target accuracy)

8 Ideal T/H – 8 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 Sufficient tracking bandwidth → negligible tracking error Well-defined sampling instant (asserted by clock rising/falling edge) Zero track-mode and hold-mode offset errors

9 T/H Errors (Track Mode) – 9 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 Finite tracking bandwidth → tracking error, T/H memory Track-mode offset, gain error, and nonlinearity

10 Acquisition Time (t acq ) – 10 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 Short L, thin t ox, large W, large V ov, and small V i help reduce R on Accuracyt acq 1% (7b) ≥ 5  0.1% (10b) ≥  0.01% (13b) ≥ 

11 T/H Errors (T-to-H Transition) – 11 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 Pedestal error (often signal-dependent) resulted from switch turn-off nonidealities (clock feedthrough and charge injection) Aperture delay – the delay Δt b/t hold command and hold action Aperture jitter – the random variation in Δt (i.e., sampling clock jitter)

12 Switch Non-Idealities – 12 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 Clock feedthrough (CF)Charge injection (CI) Fast turn-off Slow turn-off

13 Pedestal Error of Top-Plate T/H – 13 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 Slow turn-off: Fast turn-off: Watch out for nonlinear errors!

14 Speed-Accuracy Tradeoff of T/H – 14 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 Pedestal error: TBW: Therefore: Technology scaling improves T/H performance!

15 Aperture Delay (Δt) – 15 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 Fixed aperture delay is usually not of problem in a single-path T/H Non-uniform aperture delays among time-interleaved T/H paths cause significant errors (Δt 1, Δt 2 … are also called sampling clock skew)

16 Aperture Jitter – 16 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 Ref: M. Shinagawa, Y. Akazawa, and T. Wakimoto, “Jitter analysis of high-speed sampling systems,” IEEE Journal of Solid-State Circuits, vol. 25, issue 1, pp. 220- 224, 1990.

17 Aperture Jitter – 17 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 

18 Aperture Jitter – 18 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014

19 T/H Errors (Hold Mode) – 19 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 Hold-mode droop caused by off-switch/diode/gate leakage Hold-mode input feedthrough (i.e., due to capacitive coupling)

20 Evaluating T/H Performance – 20 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 kT/C noise: SNDR: NoiseDistortion CSCS √kT/C 100pF6.4μV 1pF64μV 10fF640μV T = 300K Jitter

21 – 21 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 MOS S/H Techniques

22 Simple Top-Plate Sampling – 22 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 Pros Simple, minimum number of devices Potentially wideband, zero track-mode offset Cons Signal-dependent tracking bandwidth Signal-dependent charge injection and clock feedthrough Signal-dependent aperture delay (sampling point)

23 Signal-Dependent Aperture Delay – 23 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 Non-uniform sampling due to signal-dependent aperture delay causes distortion in top-plate S/H Sharp clock edge and small V in mitigate the delay variation

24 Signal Distortion – 24 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014  ← 2 nd -order

25 CMOS Switch – 25 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 R on still depends on V in and is sensitive to N/P mismatch Large parasitic cap due to PMOS switch for symmetric R on Clock rising/falling edge alignment

26 Clock Bootstrapping – 26 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 Constant gate overdrive voltage V GS = V DD for the switch R on is not dependent on V in to the first order (body effect?) NMOS device only with less parasitic capacitance

27 Clock Bootstrapping – 27 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 Ref: A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline ADC,” IEEE Journal of Solid-State Circuits, vol. 34, issue 5, pp. 599-606, 1999.

28 Clock Bootstrapping (Φ=0) – 28 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014

29 Clock Bootstrapping (Φ=1) – 29 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014

30 Dummy Switch – 30 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 Initial size of dummy chosen with the assumption of a 50/50 split of Q ch ; usually (W/L) dummy < ½(W/L) switch in practice The nonlinear dependence of CI on Z i, C S, and clock rise/fall time makes it difficult to achieve a precise cancellation Ф_ rising edge must trail Ф falling edge

31 Balanced Switch + Dummy – 31 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 Ref: L. A. Bienstman and H. J. De Man, “An eight-channel 8 bit microprocessor compatible NMOS D/A converter with programmable scaling,” IEEE Journal of Solid- State Circuits, vol. 15, issue 6, pp. 1051-1059, 1980. TBW Parasitics

32 Fully-Differential T/H – 32 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 All even-order distortions cancelled, including the signal-dependent aperture delay-induced distortion Actual cancellation limited by P/N mismatch (1-10% typically) f in 0.5GHz V DD 1.8V tftf 0.1ns A (V in )0.5V SDR (SE)20-30 dB SDR (DF)40-50 dB E.g.

33 Bottom-Plate Sampling – 33 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 AC-ground switch opens slightly earlier than input switches Signal-independent CF and CI of switch Φ e to the first order! Input switch can be further bootstrapped Typical for applications of more than 8-bit resolution Less tracking bandwidth due to more switches in series Signal swing at node X is not entirely zero!

34 – 34 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 Sample-and-Hold Amplifier (SHA)

35 Inverting SHA – 35 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 Inverting, closed-loop gain determined by the ratio C S /C H CMOS or bootstrapped switches are required when passing signals with large swing (where?)

36 Inverting SHA (Track-Mode) – 36 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 CF and CI are independent of V in and cancelled differentially Φ 1e switch is equivalent to two switches of half channel length → faster, less CF and CI

37 Inverting SHA (Hold-Mode) – 37 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 For 1X gain (C S = C H ), the feedback factor is about 1/2 Floating switch Φ 2 in hold-mode → flexible input common mode Useful for single-ended to differential conversion CM? DM?

38 Differential Mode – 38 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 DM charge transfer is complete DM half circuit 

39 Common Mode – 39 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 CM charge is not transferred! CM half circuit 

40 Flip-Around SHA – 40 – Data Converters Sample-and-HoldProfessor Y. Chiu EECT 7327Fall 2014 Non-inverting, 1X closed-loop gain Close-to-unity feedback factor in hold mode CF/CI independent of V in and cancelled differentially


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