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嵌入式微處理機 Embedded Processors 國立中興大學 電機工程學系 微控實驗室 蔡智強.

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Presentation on theme: "嵌入式微處理機 Embedded Processors 國立中興大學 電機工程學系 微控實驗室 蔡智強."— Presentation transcript:

1 嵌入式微處理機 Embedded Processors 國立中興大學 電機工程學系 微控實驗室 蔡智強

2 Info NCHUEE 720A Lab Prof. Jichiang Tsai  Time : Mon. 6, 7, 8 (Lab 501)  Evaluation :  Lab 40%  Mid term 30%  Term Project 30%  Website :  Text Book: AM335x ARM® Cortex™-A8 Microprocessors (MPUs) Technical Reference Manual  References: BeagleBone Rev A6 System Reference Manual AM335x ARM® Cortex™-A8 Microprocessors (MPUs)

3 Outline NCHUEE 720A Lab Prof. Jichiang Tsai  Introductory Overview  ARM Cortex-A8 Architecture  Power, Reset, and Clock Management  General-Purpose Input/Output  Interrupts  Timers  Universal Asynchronous Receiver/Transmitter (UART)  I2C  Memory Subsystem

4 Outline (cont.) NCHUEE 720A Lab Prof. Jichiang Tsai  Enhanced Direct Memory Access (EDMA)  Pulse-Width Modulation Subsystem (PWMSS)  Controller Area Network (CAN)  Control Module  Multichannel Serial Port Interface (McSPI)  LCD Controller  Universal Serial Bus (USB)

5 Lecture 1 Introductory Overview NCHUEE 720A Lab Prof. Jichiang Tsai

6 BeagleBone Development Board NCHUEE 720A Lab Prof. Jichiang Tsai  Processor  The board currently uses either the AM3359 or AM3358 processor in the 15x15 package  Actual processor speed is determined by the actual devices supplied  Memory  A single 16 bit DDR2 memory device is used  The design supports 128MB or 256MB of memory  The standard configuration is 256MB at 400MHz  A single 32KB EEPROM is provided on I2C0 that holds the board information  This includes board name, serial number, and revision information  Unused areas can be used by SW applications if desired

7 BeagleBone Development Board (cont.) NCHUEE 720A Lab Prof. Jichiang Tsai  Power Management  The TPS65127B power management device is used  Along with a separate LDO (Low Dropout Regulator) to provide power to the system  PC USB Interface  An onboard USB HUB that concentrates two USB ports  USB to serial debug  Provided via UART0 on the processor using a dual channel FT2232H USB  USB to JTAG  The second port on the FT2232H is used for the JTAG port  USB processor port access  When connected to the PC, each of these will show up as ports on the PC  The HUB connects directly to the USB0 port on the processor

8 BeagleBone Development Board (cont.) NCHUEE 720A Lab Prof. Jichiang Tsai  MicroSD Connector  The board is equipped with a single microSD connector  To act as the primary boot source for the board  A 4GB microSD card is supplied with each board  USB1 Port  A single USB Type A connector with full LS/FS/HS Host support connects to USB1 on the processor  The port can provide power on/off  Able to add a HUB for standard keyboard and mouse interfacing  USB Client Port  Access to USB0 is provided via the onboard USB Hub  It will show up on a PC as a standard USB device

9 BeagleBone Development Board (cont.) NCHUEE 720A Lab Prof. Jichiang Tsai  Power Sources  The board can be powered from a USB port on a PC or from an optional 5VDC power supply  When powered from USB, the board is limited to 500 MHz  For 720 MHz operation, DC power is required  Reset Button  When pressed and released causes a reset of the board  Indicators  There are five total green LEDs on the board:  One power LED indicates that power is applied  Four Green LEDs can be controlled via the SW by setting GPIO ports

10 BeagleBone Development Board (cont.) NCHUEE 720A Lab Prof. Jichiang Tsai

11 BeagleBone Development Board (cont.) NCHUEE 720A Lab Prof. Jichiang Tsai

12 BeagleBone Development Board (cont.) NCHUEE 720A Lab Prof. Jichiang Tsai

13 BeagleBone Development Board (cont.) NCHUEE 720A Lab Prof. Jichiang Tsai

14 Expansion Interface NCHUEE 720A Lab Prof. Jichiang Tsai  Two 46 pin dual row female headers are supplied on the board for access to the expansion signals  Some functionality is accessible from the expansion header  LCD  A full 24 bit LCD panel can be supported  With the backlight and touchscreen functionality  GPMC (General Purpose Memory Controller)  Access to the GPMC bus is provided  This may result in the loss of the LCD interface  MMC1 (Multimedia Card 1)  MMC1 signals are exposed on the expansion headers

15 Expansion Interface (cont.) NCHUEE 720A Lab Prof. Jichiang Tsai  SPI  There are two SPI ports available on the expansion header  SPI0 has one CS signal and SPI1 has two CS signals  I2C  There are two I2C Ports on the expansion header: I2C1 and I2C2  I2C2 is used for the EEPROMS on the expansion boards  It must always be accessible  SW should never mess with these signals  Serial Ports  There are four serial ports on the expansion headers  UART ports 1, 2, 4 ports have TX, Rx, RTS and CTS signals  UART5 only has TX and RX

16 Expansion Interface (cont.) NCHUEE 720A Lab Prof. Jichiang Tsai  A/D Converters  Seven 100K sample per second A to D converters are available  Level shifters will be required  These signals connect direct to the processor  The VDD_ADC voltage is 1.8V  It is not to be used to power anything  It is only a reference voltage  GPIO  A maximum of 66 GPIO pins are accessible  All of these pins are 3.3V and can be configured as inputs or outputs  Any GPIO can be used as an interrupt  It is limited to two interrupts per GPIO Bank  For a maximum of eight pins as interrupts

17 Expansion Interface (cont.) NCHUEE 720A Lab Prof. Jichiang Tsai  CAN Bus  There are two can bus interfaces available  Supporting CAN version 2 parts A and B  The TX and RX digital signals are provided  TIMERS  There are four timer outputs on the expansion header  PWM  There are up to eight PWM outputs on the expansion header  High Resolution Outputs  Up to 6 single ended  ECAP (Enhanced Capture) PWM- 2 outputs

18 AM335x Microprocessor NCHUEE 720A Lab Prof. Jichiang Tsai

19 AM335x Microprocessor (cont.) NCHUEE 720A Lab Prof. Jichiang Tsai  Up to 800-MHz ARM® Cortex™-A8 32-Bit RISC Microprocessor  NEON™ SIMD Coprocessor  32KB of L1 Instruction and 32KB Data Cache  With Single-Error Detection (parity)  256KB of L2 Cache with Error Correcting Code (ECC)  176KB of On-Chip Boot ROM  64KB of Dedicated RAM  On-Chip Memory (Shared L3 RAM)  mDDR (LPDDR), DDR2, DDR3, DDR3L Support  General-Purpose Memory Support (NAND, NOR, SRAM)  Supporting Up to 16-bit ECC

20 AM335x Microprocessor (cont.) NCHUEE 720A Lab Prof. Jichiang Tsai  SGX530 3D Graphics Engine  LCD and Touchscreen Controller  Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS)  Real-Time Clock (RTC)  Up to Two USB 2.0 High-Speed OTG Ports  With Integrated PHY  10, 100, 1000 Ethernet Switch  Supporting Up to Two Ports

21 AM335x Microprocessor (cont.) NCHUEE 720A Lab Prof. Jichiang Tsai  Serial Interfaces  Two Controller Area Network Ports (CAN)  Six UARTs, Two McASPs (Multichannel Audio Serial Ports)  Two McSPI, Three I2C Ports  Interrupt Controller (up to 128 interrupt requests)  12-Bit Successive Approximation Register (SAR) ADC  Up to Three 32-Bit Enhanced Capture Modules (eCAP)  Up to Three Enhanced High-Resolution PWM Modules (eHRPWM)  Crypto Hardware Accelerators (AES, SHA, PKA, RNG)


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