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The Intel Microprocessors Chapter 2 The Microprocessor and its Architecture Instructor : Dr. Yu Youling.

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Presentation on theme: "The Intel Microprocessors Chapter 2 The Microprocessor and its Architecture Instructor : Dr. Yu Youling."— Presentation transcript:

1 The Intel Microprocessors Chapter 2 The Microprocessor and its Architecture Instructor : Dr. Yu Youling

2 Outline Internal Microprocessor ArchitectureInternal Microprocessor Architecture Real Model Memory AddressingReal Model Memory Addressing 第2页第2页

3 The CPU The Central Processing Unit (CPU) is a fundamental component of a PC system (No CPU  No Computer)The Central Processing Unit (CPU) is a fundamental component of a PC system (No CPU  No Computer) Basically it is a complex microprocessor whose main task is to process data stored in an external memory (RAM) according to instructions also stored within that external memoryBasically it is a complex microprocessor whose main task is to process data stored in an external memory (RAM) according to instructions also stored within that external memory Additionally, however, CPUs also generally contain some special fast internal storage memory, called registersAdditionally, however, CPUs also generally contain some special fast internal storage memory, called registers 第3页第3页

4 The CPU Components Basic ComponentsBasic Components –Registers & Flags –Arithmetic Logic Units –Shifters / Rotators –Address Decoding Modules Advanced ComponentsAdvanced Components –Math. Co-processors –Data & Program Pipelines –Caches –Micro-code instruction decoders. –Multimedia Extension Processors. (MMX) –Etc 第4页第4页

5 Registers Registers can be used by a programmer/user like a ‘scratch pad’ to carry out calculations or other tasks performed within the CPURegisters can be used by a programmer/user like a ‘scratch pad’ to carry out calculations or other tasks performed within the CPU All of the 8086 family of CPUs have 14, 16-bit registers that are commonly used and are at the disposal of the userAll of the 8086 family of CPUs have 14, 16-bit registers that are commonly used and are at the disposal of the user Starting with the 80386, Intel also added a new set of 32- bit registers and instructions to the CPUStarting with the 80386, Intel also added a new set of 32- bit registers and instructions to the CPU For this course, however, we are only going to focus on what Intel refer to as the Real Mode operation of the CPUFor this course, however, we are only going to focus on what Intel refer to as the Real Mode operation of the CPU 第5页第5页

6 Real Mode Memory Addressing The special mode called Real Mode switches any 8086 family CPU into an 8086 compatibility mode (even Pentium IVs have this mode implemented)The special mode called Real Mode switches any 8086 family CPU into an 8086 compatibility mode (even Pentium IVs have this mode implemented) In this mode the user is allowed access only to 14 basic 16-bit registers, 1Mb of RAM and 64 Kb of I/O spaceIn this mode the user is allowed access only to 14 basic 16-bit registers, 1Mb of RAM and 64 Kb of I/O space Once this area has been mastered, the basic skills and knowledge required to master the more advanced CPUs like the 80386, 80486, Pentiums, Pentium IIs with MMX, etc. will have been developedOnce this area has been mastered, the basic skills and knowledge required to master the more advanced CPUs like the 80386, 80486, Pentiums, Pentium IIs with MMX, etc. will have been developed 第6页第6页

7 1MB RAM In real mode, 8086 family CPUs are able to access a total of 1 MB of RAMIn real mode, 8086 family CPUs are able to access a total of 1 MB of RAM Conceptually this can be thought of as a contiguous block from 00000h  FFFFFhConceptually this can be thought of as a contiguous block from 00000h  FFFFFh In practice, however, this memory is segmented into 64Kb blocks, i.e. blocks from 0000h  FFFFhIn practice, however, this memory is segmented into 64Kb blocks, i.e. blocks from 0000h  FFFFh This was done to maintain compatibility with Intel’s early 8085 processors, which had only 16 address lines providing access to 64 Kb of memory (216 = 64K)This was done to maintain compatibility with Intel’s early 8085 processors, which had only 16 address lines providing access to 64 Kb of memory (216 = 64K) 第7页第7页

8 General Purpose Registers 第8页第8页

9 General Purpose Registers General Purpose RegisterGeneral Purpose Register –for arithmetic calculations, temporary data storage, data transfer, etc –EAX: Accumulator: Referenced as EAX, AX, AL or AH. The most commonly used registerThe most commonly used register Used by string instructions (STOSB, STOSW, etc.) to hold the data being transferredUsed by string instructions (STOSB, STOSW, etc.) to hold the data being transferred Used by I/O instructions (IN, OUT) to hold the data being transferredUsed by I/O instructions (IN, OUT) to hold the data being transferred Used by multiply (MUL) and divide (DIV) to contain the data before the instruction and the result afterUsed by multiply (MUL) and divide (DIV) to contain the data before the instruction and the result after Used by string instructions and BIOS to hold the ASCII and ATTRIBUTE values when writing to the screen in text modeUsed by string instructions and BIOS to hold the ASCII and ATTRIBUTE values when writing to the screen in text mode 第9页第9页

10 General Purpose Registers General Purpose RegisterGeneral Purpose Register –EBX: Base Index: Used by several addressing mode instructions to hold the base of a block of data to be manipulated.Used by several addressing mode instructions to hold the base of a block of data to be manipulated. A block usually contains some related data, e.g. a message to print in ASCIIA block usually contains some related data, e.g. a message to print in ASCII –ECX: Count: Used by instructions such as REP and LOOP as a counter, e.g if CX = 10 then the LOOP instruction will loop 10 times decreasing CX until it reaches zeroUsed by instructions such as REP and LOOP as a counter, e.g if CX = 10 then the LOOP instruction will loop 10 times decreasing CX until it reaches zero Also used by the Shift (SHR, SHL) and Rotate (ROR, ROL) instructions to indicate how many bits to shift or rotateAlso used by the Shift (SHR, SHL) and Rotate (ROR, ROL) instructions to indicate how many bits to shift or rotate 第 10 页

11 General Purpose Registers General Purpose RegisterGeneral Purpose Register –EDX: Data: Used by I/O (IN, OUT) instructions to hold the address of the port being accessedUsed by I/O (IN, OUT) instructions to hold the address of the port being accessed Used by the Multiply (MUL) and Divide (DIV) instructions to hold the result of 32-bit data manipulationsUsed by the Multiply (MUL) and Divide (DIV) instructions to hold the result of 32-bit data manipulations Also used by BIOS to set up cursor positionsAlso used by BIOS to set up cursor positions 第 11 页

12 General Purpose Registers ESP: Stack Pointer:ESP: Stack Pointer: –Used by the stack, call and return instructions. EBP: Base Pointer:EBP: Base Pointer: –Holds the base pointer for memory data transfers. EDI: Destination Index:EDI: Destination Index: –Holds the base destination pointer for string instructions. ESI: Source Index:ESI: Source Index: –Holds the base source pointer for string instructions 第 12 页

13 General Purpose Registers EIP: Instruction Pointer:EIP: Instruction Pointer: –register that points to the next instruction to be executed in the RAM –If a 2 byte instruction is currently being executed at 0100, then IP = 0102 –IP has a range from 0000 (0000 decimal) to FFFF (65535 decimal) –This means that the CPU can only access up to 64K bytes of instructions using the IP register alone –Always works in conjunction with the CS register to generate a physical address 第 13 页

14 General Purpose Registers EIP: Instruction Pointer:EIP: Instruction Pointer: –Certain program instructions may alter it in order to cause execution of a different section of code –Jump instructions alter IP to point to a new instruction to jump to next –Call instructions also alter IP to indicate a new location to start executing from, but the current value of IP is saved to allow a return to the current next instruction –Interrupts alter this register, setting it to point to the location of the relevant ISR code 第 14 页

15 Special Purpose Registers EFLAGS:EFLAGS: –Store the state of various conditions in the microprocessor. –The rightmost 5 flag bits and overflow change after many of the arithmetic and logic instructions execute. Data transfer and program control instructions never change the flags 第 15 页

16 Flag bits C (Carry):C (Carry): –Holds the carry out after addition or the borrow after subtraction. –Also indicates error conditions. P (Parity):P (Parity): –0 for odd number of bits ( 奇数 ) and 1 for even( 偶数 ). –Obsolete feature of the 80x86. A (Auxiliary Carry):A (Auxiliary Carry): –Highly specialized flag used by DAA and DAS instructions after BCD addition or subtraction 第 16 页

17 Flag bits Z (Zero):Z (Zero): –1 if the result of an arithmetic or logic instruction is 0. S (Sign):S (Sign): –1 if the sign of the result of an arithmetic or logic instruction is negative. T (Trap):T (Trap): –Trap enable. The microprocessor interrupts the flow of instructions on conditions indicated by the debug and control registers 第 17 页

18 Flag bits I (Interrupt):I (Interrupt): –Controls the operation of the INTR (Interrupt request) pin. If 1, interrupts are enabled. Set by STI and CLI instructions. D (Direction): D (Direction): –Selects with increment or decrement mode for the DI and/or SI registers during string instructions. If 1, registers are automatically decremented. Set by STD and CLD instructions. O (Overflow):O (Overflow): –Set for addition and subtraction instructions 第 18 页

19 Flag bits and up:80286 and up: –IOPL (I/O privilege level): It holds the privilege level at which your code must be running in order to execute any I/O-related instructions. 00 is the highest.It holds the privilege level at which your code must be running in order to execute any I/O-related instructions. 00 is the highest. –NT (Nested Task): Set when one system task has invoked another through a CALL instruction in protected mode.Set when one system task has invoked another through a CALL instruction in protected mode 第 19 页

20 Flag bits and up:80386 and up: –RF (Resume): Used in debugging.Used in debugging. –VM (Virtual Mode): When 0, the CPU can operate in Protected mode, Virtual 8086 mode or Real mode.When 0, the CPU can operate in Protected mode, Virtual 8086 mode or Real mode. When set, the CPU is converted to a high speed This bit has enormous impact.When set, the CPU is converted to a high speed This bit has enormous impact 第 20 页

21 Flag bits 80486SX and up:80486SX and up: –AC (Alignment Check): Specialized instruction for the 80486SX.Specialized instruction for the 80486SX. Pentium and up:Pentium and up: –VIF (Virtual Interrupt Flag): Copy of the interrupt flag bit.Copy of the interrupt flag bit. –VIP (Virtual Interrupt Pending): Provides information about a virtual mode interrupt.Provides information about a virtual mode interrupt. –ID (Identification): Supports the CPUID instruction, which provides version number and manufacturer information about the microprocessor.Supports the CPUID instruction, which provides version number and manufacturer information about the microprocessor 第 21 页

22 Segment Registers CS (Code Segment):CS (Code Segment): –In real mode, this specifies the start of a 64KB memory segment. –In protected mode, it selects a descriptor. –The code segment is limited to 64KB in the and 4 GB in the 386 and above. DS (Data Segment):DS (Data Segment): –Similar to the CS except this segment holds data. ES (Extra Segment):ES (Extra Segment): –Data segment used by some string instructions to hold destination data. SS (Stack Segment):SS (Stack Segment): –Similar to the CS except this segment holds the stack. –ESP and EBP hold offsets into this segment. FS and GS: and up.FS and GS: and up. –Allows two additional memory segments to be defined 第 22 页

23 Real Mode Memory Addressing Used because IP is only 16-bits long whereas the total addressable RAM space is 2 20 = 1M = in sizeUsed because IP is only 16-bits long whereas the total addressable RAM space is 2 20 = 1M = in size The actual physical address in RAM is calculated as (SEGMENT * 16) + IP, i.e. Segment & OffsetThe actual physical address in RAM is calculated as (SEGMENT * 16) + IP, i.e. Segment & Offset –e.g. if CS = 07A0 and IP = 0100 then the physical address = 07A = 07B00 NoteNote –More than one segment pointer combination can point to the same physical address –e.g. 07B00 = 07A0:0100 or 07B0: 第 23 页

24 Real Mode Memory Addressing Only mode available to the 8086 and 8088.Only mode available to the 8086 and –Allow the processor to address only the first 1MB of memory. –DOS requires real mode. Segments and Offsets:Segments and Offsets: –Effective address = Segment address + an offset 第 24 页

25 Real Mode Memory Addressing Segments and Offsets:Segments and Offsets: –Syntax is usually given as seg_addr:offset, e.g. 1000:F000 in the previous example to specify 1F000H. Default Segment and Offset RegistersDefault Segment and Offset Registers –Implicit combinations of segment registers and offsets are defined for memory references. –For example, the code segment (CS) is always used with the instruction pointer (IP for real mode or EIP for protected mode). CS:EIPCS:EIP SS:ESP, SS:EBPSS:ESP, SS:EBP DS:EAX, DS:EBX, DS:ECX, DS:EDX, DS:EDI, DS:ESI, DS:8- bit_literal, DS:32-bit_literalDS:EAX, DS:EBX, DS:ECX, DS:EDX, DS:EDI, DS:ESI, DS:8- bit_literal, DS:32-bit_literal ES:EDIES:EDI FS and GS have no default.FS and GS have no default. It is illegal to place an offset larger than FFFF into the bit registers operating in Real Mode.It is illegal to place an offset larger than FFFF into the bit registers operating in Real Mode 第 25 页

26 Real Mode Memory Addressing Segments and Offsets:Segments and Offsets: –Segments can overlap, as shown below for the CS and DS. –Segmented addressing allows relocation of data and code. –OS can assign the segment addresses at run time 第 26 页

27 第 27 页

28 Defaults Default 16-bit addresses are programs in CS, stack data in SS, and most other data in a program in DS.Default 16-bit addresses are programs in CS, stack data in SS, and most other data in a program in DS. Default 32-bit addresses are programs in CS, stack data in SS and most other data in DS.Default 32-bit addresses are programs in CS, stack data in SS and most other data in DS. What’s the difference?What’s the difference? –16-bit addresses use offset addresses in BX, SI, DI, BP, or an offset numeric value –32-bit addresses use offset addresses in EAX, EBX, ECX, EDX, EBP, EDI, ESI or a numeric value. Programs resides in segment CS addressed by IP/EIPPrograms resides in segment CS addressed by IP/EIP Stack data resides segment SS addressed by SP/ESPStack data resides segment SS addressed by SP/ESP

29 Effective Address Calculations EA = segment x 10H plus offsetEA = segment x 10H plus offset (a) = (b) ABC34 = AAF (c) 21FF0 = FFF0 Example (a) contained 1000 in the segment register, example (b) contained a AAF0 in the segment register, and example (c) contained a 1200 in the segment register.

30 Relocation Segment and offset addressing allows for easy and efficient relocation of code and data.Segment and offset addressing allows for easy and efficient relocation of code and data. To relocate code or data only the segment number needs to be changed. For example, if an instruction appears at offset address 0002 the segment address does not matter because if it changes so does the effective address of the instruction.To relocate code or data only the segment number needs to be changed. For example, if an instruction appears at offset address 0002 the segment address does not matter because if it changes so does the effective address of the instruction.

31 Homework 第一部分 第一部分 –8,10,13,14,20 第二部分(任选一,中文, 500 字) 第二部分(任选一,中文, 500 字) – 通过互联网,查询并简要写出保护模式的工作原理 – 通过互联网,查询并简要写出分页机制的工作原理 第 31 页


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