2 Early microprocessors PMOS technology – slow and awkward to interface with TTL family4 bit processorInstructions were executed in about 20 µs.Intel 4004 the first MP. 4K nibbles address space.Intel can manipulate a whole byte.16Kbytes address space50,000 operations/second.
3 N-channel MOSFET 1970. Faster than P-MOS. Work with +ve supply; easy to interface with TTL.1973 Intel 8080 MP.500,000 operations/second.64K bytes memory.Upward software compatible with 8008.Other brands are MC6800, Fairchild’s F-8 etc.
4 Basic types of MP Two types Single component microprocessors Bit sliced microprocessorsCan be cascaded to allow functioning systems with word size from 4 bits to 200 bits.
5 Single component M Computer Composed ofA processorread only memory (for program storage)Read/Write memory (for data storage)Input/output connections for interfacingTimer as event counterIntel 8048, Motorola 6805R2.Oven, washing machine, dish washer etc.
6 Modern MP 8, 16, 32, 64 bits are available. Intel 8085, Motorola 6800 – 8 bit word 16 bit address.Intel 8088, 8086, Motorola – 16 bits word, 20 bits address.80186 – never used.286 – real mode and protected mode; 16MB memory386 – paging, 4GB memory, 32 bits word486 – math coprocessor, L1 cache
7 Modern MP Pentium Pentium Pro Pentium MMX Pentium II, III, IV RISC 64 bits i/o off the chip but process 32bits word, exception floating point processed 64 bits, cache doubled, instruction pipelining.Pentium ProL2 cache, Improved pipeliningPentium MMXMulti-Media extensions, 57 new inter instruc mostly used for multimedia programmingPentium II, III, IVPentium pro with MMX tech, increased L2 cache, full 64 bit operationRISCReduced instruction set processor, uniform length instruc, faster in operation, cannot perform may different thing as CISC.
9 Basic MP architecture Fetch, decode, execute. PC increment. First instruction is a fetch0000H for 8085FFFF0H for 8086, 8088Data BusAF, BC, DE, HL, SP, PCmany moreInstructionRegisterRegister ArrayALUControlBuscontrolAddress Bus
11 Interfacing needs busIsolation and separation of signals from different devices connected to MP.UnidirectionalBidirectionalLS373, 244
12 Memory mapPictorial representation of the whole range of memory address space.Defines which memory system is where, their sizes etc.Address space or range.8086 has 1M address space in minimum mode.8085 has 64K address sspace.
13 Address DecodingAddress decoder is a digital ckt that indicates that a particular area of memory is being addressed, or pointed to, by the MP.Absolute address decodingDecode an address to one single outputDecode so that u can get a signal from the decoder when it receives exactly that bit pattern.Partial address decodingSome bits are used as don’t care so that decoder gives a signal for a range of consecutive bit patterns.
14 Absolute decoding 1 0 1 1 0 a b c d e 1 0 1 1 0 Active low o/p signal Active low o/p signala b c d eCan use decoder IC with gates to achieve exact decoded o/p3 to 8 line dcdo/pLogic 178 input NAND gate implementation
15 Partial decodingWhen a range of addresses are deconded then it is called partial decoding. For example, if we need to generate a control signal for an address generated by the MP within the range FFF0 – FFFF, then it is called partial decoding.Decoder, multiplexer can be used for address decodingA15A14x x x xA4
17 Interfacing A Memory Chip 2K Byte memoryMemory address space of the chip:8800H to 8FFFHA14IO/MA15A133 to 8decoderE1 E2 E3A12MEMSELQ1A11A10MemoryChipCED7A9D6A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0X X X X X X X X X X XA0D088 - F0 - F0 - FRDWR
18 Reading a byte from memory Reading an Opcode 4Fh in memory location 2005H.PC places the 16bit address 2005H of the memory location on the address bus.Control unit sends the memory read signal (MEMR) to enable O/P buffer of the memory chip.The value 4Fh stored in location 2005H is placed on the data bus and transferred to instruction decoder of the MP.
20 MP operations MP initiated Operations Internal operations Memory/IO read/writeInternal operationsStore 8-bit dataArithmetic and logical operationsTest for conditionsSequence the execution of InstructionStack operationPeripheral operationsReset, Interrupt, ready and hold
21 Flag registerS : after the execution of an arithmetic operation, if bit 7 of the result is 1, then sign flag is set.Z : bit is set if ALU operation results a zero in the Acc or registers.AC: bit is set, when a carry is generated by bit 3 and passed on bit 4.P: parity bit is set when the result has even number of 1s.CY = carry is set when result generates a carry. Also a borrow flag.SZACPCY
22 Accumulator Hold data for manipulation (arithmetic, logical). Whenever the operation combines two words, either arithmetically or logically, the accumulator contains one word (say A) and the other word (say B) may be contained in a register or in memory location. After the operation the result is placed in the Acc replacing the word A.Major working register. MP can directly work on Acc.Programmed data transfer.
23 General purpose registers Six registers.B, C, D, E, H and L can store 8 bit data.They can be combined to perform some 16 bit operation.
24 ALU Arithmetic logic unit. Two input ports, one output port. Perform AND, OR, ExOR, Add, subtract, complement, Increment, Decrement, shift left, shift right.ALUs one temporary registers are connected to MPs internal bus from which it can take data from any registers. It can place data directly to data bus through its single output port.
25 Program counterIts job is to keep track of what instruction is being used and what the next instruction will be.For 8085 it is 16 bit long.Can get data from internal bus as well as memory location.PC automatically increments to point to the next memory during the execution of the present instruction.PC value can be changed by some instructions.
26 Stack pointer 16 bit register acts as memory pointer. Can save the value of the program counter for later use.points to a region of memory which is called stack. follows LIFO algorithm.After every stack operation SP points to next available location of the stack. Usually decrements.
27 Memory address register PC sends address to MAR. MAR points to the location of the memory where the content is to be fetched from.PC increments but MAR does not.If the content is an instruction, IR decodes it. During execution if it is required to fetch another word from memory, PC is loaded with the valuePC again sends it to the MAR and fetch operation starts.
28 Instruction registerHolds instruction the microprocessor is currently being executed.8 bit long.
29 othersInstruction decoder.Control logic.Internal data bus.
30 Machine cycle and Timing dia MP works in steps of clock. Each clock cycle is called T-state.A machine cycle is composed a few T-states and performs either read or write operations.All MP instructions are divided into few machine cycles.Opcode fetchMemory readMemory writeIO readIO write
31 Timing diaga. of Memory cycle CLKA15-A8A7-A0Data from memoryAD7-AD0A7-A0Data from MPUALEIO/MRDWRMEMRDMEMWRREAD CycleWRITE Cycle
33 Execution time Clock frequency f = 2 MHz T-state = (1/f) = 0.5 µs Exec time for opcode fetch= (4Tx0.5)=2 µs.Exec time for memory read = 3Tx0.5=1.5 µs.Exec time for instruction = 7Tx0.5 = 3.5 µs.
34 8085 40 pin DIP. +5V 3 - 5MHz ADD BUS DATA BUS CONTROL STATUS GND402021 – 28HIGH ORDERADD BUSX1 X240 pin DIP.+5V3 - 5MHzADD BUSDATA BUSCONTROL STATUSPOWER SUPPLY AND FREQEXTERNALLY INITIATED SIGNALSSERIAL I/O PORTSSID 5SOD 4TRAP 612 – 19MUX ADD/ DATA BUSRST7.5 7RST6.5 8RST5.5 9INTR 1030 ALE29 S0READY 35HOLD 3933 S1RESET IN 3634 IO/M’32 RD’INTA 11HLDA 3831 WR’RESET OUTCLK OUT
35 crystal, LC tuned, external clock ckt. 8085 has the clock generation circuit on the chip can operate maximum 3.03 MHz and 8085A-2 can operate maximum 5 MHz clock.crystal, LC tuned, external clock ckt.the frequency at x1x2 is divided by 2 internally. This means that in order to obtain 3.03MHz, a clock source of 6.06MHz must be connected to X1X2.for crystals with less than 4MHz, a capacitor of 20pF should be connected X2 and ground.X1X2GNDX1X2
36 ADD/DATA bus Address bus 16 bits Data bus 8 bit long: AD0 to AD7 Q’OCAD7AD6AD5AD0ALEGNDAddress bus. Lower 8 bitAddress bus. higher 8 bitA8A15Address bus 16 bitsA8 to A15 unidirectional. Higher 8 bitAD0 to AD7 multiplexed with data. This pins are bidirectional when used as data bus.Data bus 8 bit long: AD0 to AD7
37 Control signalsALE – active high output used to latch the lower 8 address bits.RD, WR - active low output signals.IO/M – output signal to differentiate memory and IO operation.S1 and S0 – status output signal. Identify various operations.Machine cycleIO/M’S1S0Control signalsOpcode fetch1RD=0Memory readMemory writeWR=0I/O readI/O writeInterrupt AcknINTA=0HaltZRD, WR =Z and INTA=1HoldXReset
38 External control signals INTR – interrupt request. Input signalINTA – interrupt acknowledge. o/p signal.RST7.5,RST 6.5, RST5.5 – restart interrupts. Vectored interrupts. Higher priority.TRAP - Nonmaskable interrupt. Highest priority.Hold – request for the control of buses. I/P signalHLDA – Hold Acknowledge. O/P signalREADY – I/P signal. When low, Mp waits for integral number of clock cycles until it goes high.
39 Interfacing I/O devices Port addressTwo ways to interfaceIO mapped I/OMemory mapped IO8085IO address space 256 (i.e 28)Memory address space 64K (i.e 216)
40 Interfacing approach Port address IO mapped IO Memory Mapped IO An address where a buffer or latch is connected through which actual data transfer takes place between MP and IO device.Input port or output port.IO mapped IOThe port address of the IO devices is mapped into the IO address spacePort address is an eight bit binary number. IN/OUT instructions are used data transfer.Memory Mapped IOThe port address of the IO device is mapped into the memory address space.Port address is a 16 bit binary number. LDA, STA etc memory related instructions are used for data transfer.
41 Logic devices for interfacing Tri-state bufferAt input port74LS244: unidirectional octal buffer74LS245: bidirectional octal bufferLatchesAt output port74LS373: Octal D type latchDecoderFor address decoding, port selection, but control signal74LS138: 3-to-8 decoder most commonly used.EncoderFor interfacing keyboard74LS148: 8 to 3 priority encoder
42 Peripheral I/O instructions port address: 50H2050 D3Let input port address is 30H2150 DBOUT 50H sends acc content to I/O address 50HIN 30H reads content from I/O address 30H andstores the value in accum
43 Device selection & Data Transfer Decode the IO address.Combine it with control the signal to generate a unique IO select pulse that is generated only when both signals are asserted.Use it to activate the IO portAddress decoding can be absolute or partialAddress linesIOR orIOWDecoderNOREnableTo PeripheralsData busLatchOrTri-stateBuffer
44 IN 30H instruction M1 M2 M3 21H 21H 50H 51H ALE IO/M RD MEMRD IORD T1 CLK21Hunspecified21HA15-A8Port add 30H50HDB from memoryAD7-AD0Port addre30H51HData from AccumulaPort add 30HALEIO/MRDMEMRDIORD
45 OUT 50H instruction M1 M2 M3 20H 50H 51H IO/M ALE RD MEMRD WR IOWR T1 CLKA15-A820HPort add, 50HunspecifiedAD7-AD050HPort addreData from Accumula51HPort add 50HOpcodeD3ALEIO/MRDMEMRDWRIOWR
46 Interfacing LED for display Given port add: FFHUse octal latch as o/p port.Steps for IO select pulse:Decode FFUse IO/M to make the port I/O mapped onlyUse WR signal to write data to the port
47 * Power supply connection to the LED segments will be opposite. MVI A, dataOUT FFHHLTA7IOADRA1WRA0* To interface a 7-segment display you need to decide about the type of 7-segment: common anode or common cathode* Power supply connection to the LED segments will be opposite.* For common cathode a 0 is sent to the respective pin to lit it up.IO/MIOSEL+5 VGD7D FFD6Octal D- latchD0OE
48 Interfacing DIP switches Let port address: 07H – 00HPartial decodingMust use pull-up resistors.IN 07H instruction reads a byte into accumulator from port 07HA4A3IO/MQ0RDA73 to 8decoderE1 E2 E3A6IOSELA5OED7D1D0+5 V
49 Interfacing 7 segment LED o/p address F9hA7A6A5A4A3IO/MQ5WRA23 to 8decoderE1 E2 E3A7 A6 A5 A4 A3 A2 A1 A0A1IOSELA0+5VOED774LS377D6D0D FF7-Segment
50 8085 Interrupts 5 interrupt pins Maskable INTR RST5.5, RST6.5, RST7.5 Non-MaskableTRAP: cannot be disabled by instruction.TRAP has highest priorityOnce a interrupt is serviced all interrupts except TRAP is disabled
51 TRAP cannot be disabled by instruction Requires a High level with a leading eadge at the pin.braches to location 0024H.disabled at the falling edge of the signal at the pin.
52 RST7.5,6.5,5.5 can be enabled or disabled by SIM (Set Interrupt Mask). 7.5 – Leading edge. branches to 003CH.6.5,5.5 – High level.6.5: branches to 0034H5.5: branches to 0020H
53 INTR Interrupt process enable by writing EI.mp checks INTR line at each instruction.if INTR is high, mp completes the current instr, disables Interrupt Flip-flop, sends INTA signal.An RST instru is inserted by INTA through external hardware.Mp saves the memory address of the next instru into stack. Program control is transferred to CALL location. The service routine starts at CALL location.At the end of the subroutine Int Flag is enabled again by EI instru.The last instr of the subroutine is RET to trasfer back the prog control to its orginal address.
54 RST instructions 8 RST instructions +5v EF to data bus 1 1 1 1 1 1 1 MnemonicsBinary codeHexCall LocationD7D6D5D4D3D2D1D0RST01C70000RST1CF0008RST20010RST3DF0018RST4E70020RST5EF0028RST6F70030RST7FF0038+5v11EF to data bus11111Enable
55 Write a program to count continuously in binary with some delay between each Count. Service routine at 8070H to flush FFH five times when the interrupt occurs (on INTR lines) with some appropriate delay between flashMain programService routine8070:SERV: PUSH BPUSH PSWMVI B, 0AHMVI A, 00HFLASH: OUT PORT1CALL DELAYCMADCR BJNZ FLASHPOP PSWPOP BEIRETLXI SP, FFFFH (stack region)EIMVI A, 00HNXTCNT: OUT PORT1CALL DELAY (not defined here)INR AJMP NXTCNTRST 5 code EF+5VInterrupt instr: EFto data busD71111At 0028H JMP 8070H0028 C3002A 80111D0INTA from µP
56 Descriptionmain program initializes stack pointer at FFFF and enables the interrupts. program will count continuously from 00 to FF with some delay between each count.To interrupt the process, a switch at INTR us pushed.the processor will complete the current instruction and senses the interrupt. Say the next instruction is INR A.µP disables the interrupt flip-flop, and sends out INTA signal.INTA enables the tri-state buffer and, and RST 5 (ie EF) is placed on the data bus.µP saves the address of the INR A instruction on the stack at locations FFFE and FFFD, and the program is transferred to memory location The location 0028 has the JMP instruction to transfer the program to the service routine.
57 Description contd. The program jumps to the service routine at 8070. The service routing saves the registers that are being used in the subroutine and loads the count ten in register B to output five flashes and five blanks.the service routine enables the interrupt before returning to main program.When the service routine executes the RET instruction, the µP retrieves the address of the instruction INR A from the stack and continues the binary counting.
58 Short QuestionsIns there a minimum pulse width required for the INTR signal?17.5 T states. CALL requir 18T states. µP check INTR signal one clock period before the last T states.How long can the INTR pulse stay high?until the interrupt flip-flop is set by EI instruction in the subroutine.Can the µP be interrupted again before the completion of the first interrupt service routine?
59 Vectored interruptsTRAP, RST 7.5,6.5 and 5.5 do not require external instruction to jump to its call locations. these interrupts are called vectored interrupts.maskable interrupts are enabled by two instructions: EI and SIM.
60 SIM Set Interrupt Mask. 7 SOD 6 SDE 5 XX 4 R7.5 3 MSE 2 M7.5 1 M6.5 M5.50=available, 1=maskedno use0 = ignore mask bits1 = mask bits are enabledserial out data: ignored if bit 6 is 0if 1, Reset 7.5Enabling all interrupts:EI ; enable interruptsMVI A, 08h ; load bit patters for intrSIM ; Enables 7.5,6.5,5.5if 1, bit 7 is serial data out
61 RIM Read Interrupt Mask. read to sense the pending interrupts.RIM loads accumulator with 8 bits indicating status of the interrupt masks.RIM can also be used to read serial data.7SID6I7.55I6.54I5.53IE2M7.51M6.5M5.51 = pending1 = masked1 = Interrupt enabledSerial input data, if any
62 RIM exampleAssuming the µP is completing an RST7.5 interrupt request, check to see if RST6.5 is pending. If it is pending, enable RST6.5 without affecting any other interrupts; otherwise return to main program.RIM ; Read interrupt maskMOV B, A ; save mask infoANI 20h ;check if RST6.5 is pendingJNZ NEXT ;EIRET ; RST6.5 is not pending; return to main programNEXT: MOV A,B ;get bit pattern; RST6.5 pendingANI 0Dh ; enables RST6.5 by setting D1=0ORI 08h ;enable SIM by setting D3=1SIMJMP SERV ; Jump service routing for RST6.5 at SERV
63 DMA Direct Memory Access HOLD HLDA IO device can transfer data from (to) memory directly.When µP controlled data transfer is too slowHOLDan input high signal to this pin initiated DMA. µP releases bus in the following machine cycle. gets back the control when HOLD is low.HLDAHOLD Ackn. After releasing the bus µP sends a high signal at this pin to inform the IO device.
64 DMA contd.Usually a DMA controller sends the DMA request to MP. The processor completes the current machine cycle; floats all the bus lines, and sends a ackn signal to HLDA. DMA controller takes the control of the buses and transfer data directly to memory from the external source by-passing µP. After data transfer DMA controller sends a low signal at HOLD pin to terminate the request for DMA. MP gets back its control over the buses.AddressMPUDMA controllerMemoryIOcontrolData BusHOLDHLDA
65 8086/8088 Architecture Seven categories of signals. Max/min mode: min mode is used for single procss. Max mode is used for multiprocssTest: synchronize multiple processorsData Enable: generally connected to biriectional buffer to isolate MPU from system bus.Data tran/rcvr: controls data flow.IO or memory: indicates whether the proc cycle is memory operation or IO operation.Bus High Enable: enble the higher order byte of 16 bit dataPower & clockVCCCLKBHE/S7A19/S6A16/S3AD15AD0ALEM/IORDWRDENDT/RMuX add& status signalsGNDINTRNMIHOLDREADYRESETExternal rqstMux add and data busesResponse to External rqstINTAHOLDAControl & status signalsMultipro envrnmntTESTMN/MX
66 Max/min mode control signals PinMin modeMax mode24INTAQS1: queue status signal25ALEQS0: queue stat signal26DENS0: input sig to bus control27DT/RS1: “28M/IOS2: “29WRLock: to prvnt another proc from gaining control30HLDARQ/GT1: enable another processor to gain control31HOLDRQ/GT0: “
68 segment registers work together with general purpose register to access any memory value. For example if we would like to access memory at the physical address 12345h (hexadecimal), we should set the DS = 1230h and SI = 0045h. This is good, since this way we can access much more memory than with a single register that is limited to 16 bit values. CPU makes a calculation of physical address by multiplying the segment register by 10h and adding general purpose register to it (1230h * 10h + 45h = 12345h): by default BX, SI and DI registers work with DS segment register; BP and SP work with SS segment register. Other general purpose registers cannot form an effective address! also, although BX can form an effective address, BH and BL cannot.
69 special purpose registers IP - the instruction pointer.flags register - determines the current state of the microprocessor.IP register always works together with CS segment register and it points to currently executing instruction.
71 for example, let's assume that DS = 100, BX = 30, SI = 70 for example, let's assume that DS = 100, BX = 30, SI = 70. The following addressing mode: [BX + SI] is calculated by processor to this physical address: 100 * = by default DS segment register is used for all modes except those with BP register, for these SS segment register is used. there is an easy way to remember all those possible combinations using this chart: you can form all valid combinations by taking only one item from each column or skipping the column by not taking anything from it. as you see BX and BP never go together. SI and DI also don't go together. here are an examples of a valid addressing modes: [BX+5] , [BX+SI] , [DI+BX-4]
72 80286 16 bit Eliminates the multiplexing of buses. Has 24 bit linear address bus support 16M bytes address directly.Supports memory management through which it can support 1Gbytes of virtual memory.Protects system software from user programs, protects users’ program, and restricts access to some memory regions.Supports multiuser systems.
73 80386/48632 bit processor.Support following multiuser system requirementHigh speed of executionAbility to handle different types of tasks efficientlyLarge memory space that can be shared by multiuserAppropriate memory allocations and the management of memory accessData security and data accessLimited and selected access to part of the systemResource sharing and management
74 32bit non-multiplexed address bus Can address 4G physical memory and through a memory management unit 64 (246) terabytes of virtual memory.Two modes:real mode, and protected mode.Execution is highly pipelined.
75 80386 Programming model8-general purpose registers can be accessed as 8, 16 or 32 bit6-segment selector registers.IP can used as 16/32 bitsFlag is 31 bits but 14 are used at present.6 for data, 3 operation,2 io previl, 1 nested task, 2 for VM31157AXBXCXDXSPBPSIDICSSSDSESFSGSIPFLAGS