Presentation on theme: "EE314 Microprocessor Systems"— Presentation transcript:
1EE314 Microprocessor Systems Chapter 5Interrupt processingObjectives:The difference between hardware and software interruptsThe difference between maskable and nonmaskable interruptsInterrupt processing proceduresThe vector address tableMultiple interrupts and interrupt prioritiesSpecial function interruptsThe general requirement of all interrupt handlersBased on "An Introduction to the Intel Family of Microprocessors" by James L. Antonakos
25.2 Hardware and Software Interrupts The nonmaskable interrupt is generated by en external device, trough a rising edge on the NMI pin.Cannot be ignored by the microprocessor.Generates a Type 2 interrupt (address 0008H in the Interrupt vector table)The maskable interrupts (0…FFH) can be generated by:an external device, trough a high logic level on the INTR pin (the external device has to specify the interrupt number).Hardwareinterrupts(IF (interrupt flag) in FLAGS register enables or disables (masks) the P to accept maskable interrupts.)microprocessor itself (i.e. when trying to divide by 0), (the interrupt number is hardware defined).Software interrupts (exceptions) using the INT instruction (followed by the interrupt number (type)).Interrupt priorityDivide-error HighestINT, INTONMIINTRSingle-step Lowest
35.3 The Interrupt Vector Table (or Interrupt Pointer Table)The memory block from address to 003FF. There are 1024 bytes, each of the 256 maskable interrupts uses four bytes to store the address where the corresponding ISR (Interrupt Service Routine) begins. The ISR address for interrupt number xx is stored beginning at address xx*4, in form CS:IP. From low to high address, the bytes are stored in the order: IP low, IP high, CS low and CS high (byte swapping).Consequences:After RESET the P cannot begin running from physical addressThe first instruction is fetched at address FFFF0H.Before using an interrupt, its corresponding ISR address has to be stored in the interrupt vector table.ISRs are handled as FAR routines (both CS and IP specified).Vectors 0 to 18 are predefined, 19 to 31 are reserved by Intel, 32 to 255 are unassigned (free to use):
45.4 The Interrupt Processing Sequence Hardware INTRInternal HW Int.Software InterruptsnoyesInterrupt not acceptedIF=1IF=1yesnoInform external devices that an interrupt acknowledge cycle beganfirst INTA cycle( INTA pin = low)(Pentium -M/IO,D/C,W/R,ADS = 0)Interrupt not acceptedThe interrupt type is the operandNMIExternal devices requesting an interrupt transmits trough data bus the interrupt typeThe interrupt type is predefinedsecond INTA cycleread interrupt type on Data BusSave processor information on stack:- FLAGS register- Return address = CS:IPFetch the address of the ISR:- CS:IP from Interrupt Vector Tableat address 4*(interrupt type)Clear IF and TF (no furthermaskable interrupts allowed)ISR execution
5Return to interrupted program 5.5 Multiple InterruptsISR execution(non NMI)NMI ISR executionIRETnoyesNMIExecution of all instructionsnoNMIExecution of 1 instructionThe interrupt type is predefinedLoad processor information from stack:- Return address = CS:IP- FLAGS registerReturn to interrupted programIRETLoad processor information from stack:- Return address = CS:IP- FLAGS registerSave processor information on stack:- FLAGS register- Return address = CS:IPClear IF and TF (no furthermaskable interrupts allowed)Fetch the address of the NMI ISR
65.6 Special Interrupts generates a type 0 interrupt. 0400:1100 B MOV BL,00400:1102 F6 F3 DIV BL0400:1104 ….Divide Error: type 0, hardware generated by the P when quotient doesn’t fit in destination (division by 0)return addressSingle step: type 1, hardware generated by the P (if TF=1) after each instruction. After pushing flags onto stack, TF is cleared (IF also), so ISR itself is not interrupted. Returning after ISR, the flags are restored, another interrupt is generated after next instruction.A program example to set or reset the TF:PUSHFPOP AXOR AX,100HPUSH AXPOPFmoves FLAGS to AXPUSHFPOP AXOR AX,100HPUSH AXPOPFupdates TFmoves AX to FLAGSReplaced by INT 3 code (CCH)by setting a breakpoint.NMI: type 2, hardware generated by an external device on emergent events (i.e. power fail). Rising edge active.0400: C CMP AL,00400: JNZ XYZ0400:1104 EE OUT DX,AL0040:1105 FE C0 XYZ: INC ALBreakpoint: type 3, software generated by a single-byte instruction, INT 3.Overflow: type 4, generated by INTO instruction if OF=1.Interrupt request has to stay active until acknowledged:External maskable interrups: type via INTR pinP generates two pulses on INTA pin. During the second pulse, the external device has to put on data bus (D0…D7) the interrupt type.
75.6 Special InterruptsInterrupts may occur in unexpected moments during main program execution (i.e. between setting of a flag as result of an arithmetical instruction and the subsequent conditional jump hanging on the flag value). After returning from ISR, the main program has to continue undisturbed by changes made in P’s internal state (environment or context): flags, registers.An ISR can perform multiple functions hanging on the value of an input parameter (i.e. the value in the AH register).Before occurrence of the interrupt (usualy a software one) the value of the parameter is prepared.The corresponding ISR tests the parameter and perform the action required by its value.The interrupt acknowledge mechanism saves FLAGS and return address, but no register content.The Interrupt Service Routine (ISR) is responsible for saving all the used register’s value on stack (PUSH), and to recover it (POP) before returning.MYISR: PUSHA…POPAIRETUsually, all registers are saved (PUSHA) and recovered (POPA)
85.6 Special InterruptsA simple circuit able to place an 8-bit interrupt number (type) onto data bussecond active pulse of INTAfirst active pulse of INTAP is reading the byte on AD7…AD0INTR can deactivate after activation of INTAInterruptrequest...INTRAD7.AD0INTAINTRINTAAD7AD6AD5AD4AD3AD2AD1AD01+5V8 x 4.7K74LS244(octalbuffer)G1 G2The octal buffer outputs are three-stateData BUS is free for carrying data between P and other devices in systemThe octal buffer controls the Data BUS.
95.6 Special Interrupts A simple prioritized interrupt circuitry P is reading the byte on AD7…AD0INT 0D0H requestedA simple prioritized interrupt circuitrysecond active pulse of INTAfirst active pulse of INTAINTA deactivates INTRP interruptrequestINT2INTRINTAAD7AD6AD5AD4AD3AD2AD1AD0...INTRAD7.AD0INTA1+5V4.7KINT2 request74LS374(octalflip-flop)OEINT0INT2.INT7(priority encoder)E GS+5V4.7KD QCLRThe octal buffer outputs are three-stateData BUS is free for carrying data between P and other devices in systemThe octal buffer controls the Data BUS.
105.7 Interrupt Service Routines Simple example: one second time interval generator using a 60Hz signal on NMI; ISR for NMINMITIME: DEC COUNT ;decrement 60th’s counter, (COUNT)(COUNT)-1;(ZF)1 if (COUT)=0JNZ EXIT ;did we go to 0?, jump only if (ZF)=0MOV COUNT, 60 ;yes, reload the counter, (COUNT)3ChCALL FAR PTR ONESEC ;call ONESEC, [SP-1],[SP-2] (CS),;[SP-3],[SP-4]EXIT,(SP)(SP)-4;reverse action when return from ONESECEXIT: IRET ;(IP)[SP],[SP+1], (CS)[SP+2],[SP+3],;(FLAGS)[SP+4],[SP+5], (SP)(SP)+6,;reverse action to what;happened accepting NMI; main program slide preparing the action of NMI’s ISRMOV COUNT, 60 ;init 60th’s counter , (COUNT)3ChPUSH DS ;save current DS content , [SP-1],[SP-2] (DS),(SP) (SP)-2SUB AX, AX ;set new DS content to 0000, (AX) 0MOV DS, AX ;(DS) 0LEA AX, NMITIME ;load address of NMITIME ISR, (AX) NMITIMEMOV , AX ;store IP address in IPT, replacing regular NMI’s ISR address;, NMITIMEMOV AX, CS ;store CS address in IPT, (AX) (CS)=current code segmentMOV [0AH], AX ;[0Ah],[0Bh] (CS)POP DS ;get old DS content back, (DS) [SP],[SP+1], (SP) (SP)+2
115.7 Interrupt Service Routines Simple example: A Divide-Error HandlerIf a divide error occurs, the ISR will load AX wit 101h, and DX with 0. A error message will be displayed. The error message is in DATA segment beginning at address DIVMSG and ends wit a “$” character. The DISPMSG procedure (subroutine) (not shown) displays the character string found in DATA segment until the first “$” character. ISR address has to be loaded (not shown) at address 0000 in the IPT (INT 0).; preparing the error message in DATA segment.DATADIVMSG DB ’Division by zero attempted!$’;first character, ”D”, at address DIVMSG in DATA segment; ISR for Divide-ErrorDIVERR: PUSH SI ;save current SI content , [SP-1],[SP-2] (SI),(SP) (SP)-2MOV AX, 101h ;load result with default, (AX) 101hSUB DX, DX ;clear DX, (DX) 0LEA SI, DIVMSG ;init pointer to error message, (SI) DIVMSG;(passing parameter trough register)CALL FAR PTR DISPMSG ;output error message, [SP-1],[SP-2] (CS),;[SP-3],[SP-4]return address,(SP)(SP)-4;reverse action when return from DISPMSGPOP SI ;get old SI content back, (SI) [SP],[SP+1], (SP) (SP)+2IRET ;(IP)[SP],[SP+1], (CS)[SP+2],[SP+3] =return address =;(the address of the first instruction;after the DIV generating the error);(FLAGS)[SP+4],[SP+5], (SP)(SP)+6,;reverse action to what happened accepting INT 0
125.7 Interrupt Service Routines Simple example: An ISR with Multiple Functions; ISR for INT 20HISR20H: CMP AH, 4 ;AH must be 0-3 only;(?)(AH)-4, (ZF)1 if (?)=0, (CF)1 if (?)<0 (unsigned);(OF)1 if (?)<-128 or (?)>127,;(PF)1 if (?) contains an even number of “1”s,;(AF) if a transport from bit 3 to bit 4 occurred,;(SF) if (?)<0 (signed)JNC EXIT ;AH >3, ISR returns without any effectCMP AH, 0 ;AH = 0 ?, (?)(AH)-0, (ZF)1 if (?)=0, ...JZ ADDAB ;AH = 0, jump to add functionCMP AH, 1 ;AH = 1 ?, (?)(AH)-1, (ZF)1 if (?)=0, ...JZ SUBAB ;AH = 1, jump to subtract functionCMP AH, 2 ;AH = 2 ?, (?)(AH)-4, (ZF)1 if (?)=0, ...JZ MULAB ;AH = 2, jump to multiply functionDIVAB: DIV BL ;AH = 3, use divide functionIRETADDAB: ADD AL, BL ;add functionSUBAB: SUB AL, BL ;subtraction functionMULAB: MUL BL ;multiply function; main program has to store the address of INT 20’s ISR at address 80h in IPT.