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Intel Microprocessor Features Pentium  IIPentium  IIIPentium  4 MPR Issue June 1997April 2000Dec 2001 Clock Speed 266 MHz1GHz2GHz Pipeline Stages 12/14.

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Presentation on theme: "Intel Microprocessor Features Pentium  IIPentium  IIIPentium  4 MPR Issue June 1997April 2000Dec 2001 Clock Speed 266 MHz1GHz2GHz Pipeline Stages 12/14."— Presentation transcript:

1 Intel Microprocessor Features Pentium  IIPentium  IIIPentium  4 MPR Issue June 1997April 2000Dec 2001 Clock Speed 266 MHz1GHz2GHz Pipeline Stages 12/14 22/24 Transistors 7.5M24M42M Cache (I/D/L2) 16k/16K/-16K/16K/256K12K/8K/256K Die Size 203mm 2 106mm 2 217mm 2 IC Process 0.28  m, 4M0.18  m, 6M Max Power 27W23W67W

2 Clock distribution network with deskewing circuit (Geannopoulos and Dai 1998), Copyright © 1998 IEEE

3 Delay shift register (Geannopoulos and Dai 1998), Copyright © 1998 IEEE

4 Phase detector (Geannopoulos and Dai 1998), Copyright © 1998 IEEE

5 Clock distribution topology (Rusu and Tam 2000), Copyright © 2000 IEEE

6 Deskew buffer architecture (Rusu and Tam 2000), Copyright © 2000 IEEE

7 Digitally controlled delay line (Rusu and Tam 2000), Copyright © 2000 IEEE

8 Simulated regional clock-grid skew (Rusu and Tam 2000), Copyright © 2000 IEEE

9 Measured regional clock skew (Rusu and Tam 2000), Copyright © 2000 IEEE

10 Core and I/O clock generation (Kurd et al. 2001), Copyright © 2001 IEEE

11 Logical diagram of core clock distribution (Kurd et al. 2001), Copyright © 2001 IEEE

12 Example of local clock buffers generating various frequency, phase and types of clocks (Kurd et al. 2001), Copyright © 2001 IEEE

13 UltraSPARC Family Characteristics UltraSPARC-IUltraSPARC-IIUltraSPARC-III Year ArchitectureSPARC V9, 4-issue Die size17.7x17.8mm x12.5mm 2 15x15.5mm 2 # of transistors5.2M5.4M23M Clock Frequency167MHz330MHz1GHz Supply voltage3.3V2.5V1.6V Process 0.5  m CMOS0.35  m CMOS0.15  m CMOS Metal layers4 (Al)5 (Al)7 (Al) Power consumption<30W <80W

14 Clock distribution delay in UltraSPARC-III (Heald et al. 2000), Copyright © 2000 IEEE

15 Semidynamic flip-flop (Klass 1998), Copyright © 1998 IEEE

16 (a)Logic embedding in a semidynamic flip-flop; (b)Two-input XOR function. (Klass, 1998), Copyright © 1998 IEEE

17 Dynamic versions of semidynamic flip-flop: single-ended; Differential. (Klass 1998), Copyright © 1998 IEEE

18 UltraSPARC-III flip-flop (Heald et al. 2000), Copyright © 2000 IEEE

19 Alpha Microprocessor Features # transistors Die Size [mm 2 ] 16.8x x x x18.8 Process 0.75  m0.5  m0.35  m0.18  m Supply [V] Power [W] Clk. Freq. [MHz] Gates/Cycle

20 Alpha microprocessor final clock driver location: (a) 21064, (b) 21164, (c) (a)(b)(c)

21 21064 clock skew (Gronowski et al. 1998), Copyright © 1998 IEEE

22 21164 clock skew (Gronowski et al. 1998), Copyright © 1998 IEEE

23 21264 clock hierarchy (Gronowski et al. 1998), Copyright © 1998 IEEE

24 21264 clock skew (Gronowski et al. 1998), Copyright © 1998 IEEE

25 21364 major clock domains (Xanthopoulos et al. 2001), Copyright © 2001

26 21364, NCLK clock skew (Xanthopoulos et al. 2001), Copyright © 2001 IEEE

27 21064 modified TSPC latches (Gronowski et al. 1998), Copyright © 1998

28 21164: (a) phase-A latch, (b) phase-B latch (Gronowski et al. 1998), Copyright © 1998 IEEE (a)(b)

29 Embedding of logic into a latch: (a) TSPC latch, one level of logic; (b) latch, two levels of logic. (Gronowski et al. 1998), Copyright © 1998 IEEE (a)(b)

30 21264 flip-flop (Gronowski et al. 1998), Copyright © 1998 IEEE

31 Critical-path and race analysis for clock buffering and conditioning (Gronowski et al. 1998), Copyright © 1998 IEEE

32 Hazard-free level-sensitive polarity-hold latch

33 General LSSD configuration

34 LSSD shift register latch

35 LSSD double-latch design

36 LSSD SRL with multiplexer used in the IBM S/390 G4 processor (Sigal et al. 1997), reproduced by permission

37 Static multiplexer version of the SRL used in the IBM S/390 G4 (Sigal et al. 1997), reproduced by permission

38 A clocked storage element is used in the non-timing-critical timing macros of the IBM S/390 G4 processor (Sigal et al. 1997), reproduced by permission

39 The clock-generation element used to detect problems created with fast paths: IBM S/390 G4 processor (Sigal et al. 1997), reproduced by permission

40 The experimental IBM PowerPC processor (Silberman et al. 1998), reproduced by permission

41 The PowerPC 603 MSL (Gerosa et al. 1994), Copyright © 1994 IEEE

42 The PowerPC 603 local clock regenerator (Gerosa et al. 1994), Copyright © 1994 IEEE

43 IBM Power4 TM 64-bit processor used in IBM eServer p690. The microprocessor consists of 174 million transistors and runs at 1.3 GHz, contains two microprocessor cores, and an on- chip memory subsystem. It is fabricated in state-of-the-art IBM 0.18  CMOS SOI technology with seven levels of copper wiring (Warnock et al. 2002), reproduced by permission

44 Standard transmission-gate MSL with LSSD capability (Warnock et al. 2002), reproduced by permission

45

46 Scannable split latch with LSSD capability used in the IBM Power4 TM. Designers were allowed to tune transmission gate size and specify input and output gates (Warnock et al. 2002), reproduced by permission

47 Library MSL with integrated front-end logic gate choices (Warnock et al. 2002), reproduced by permission

48 Split-latch designs with integrated front- and back-end logic-gate choices (Warnock et al. 2002), reproduced by permission


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