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© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Chapter 1 Introduction to Microprocessors.

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Presentation on theme: "© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Chapter 1 Introduction to Microprocessors."— Presentation transcript:

1 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Chapter 1 Introduction to Microprocessors by Barry B. Brey

2 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Mechanical Computing The abacus circa 500 B.C. – the first calculator The abacus circa 500 B.C. – the first calculator Blaise Pascal – the first modern mechanical adder Blaise Pascal – the first modern mechanical adder Charles Babbage – the first true computer Charles Babbage – the first true computer Herman Hollerith – the punched card system and founder of IBM Herman Hollerith – the punched card system and founder of IBM

3 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Early electronic computers Konrad Zuse – Z3 (relay logic at 5.33 Hz) Konrad Zuse – Z3 (relay logic at 5.33 Hz) Alan Turing – Colossus Alan Turing – Colossus University of Pennsylvania - ENIAC University of Pennsylvania - ENIAC

4 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Early milestones 1948 – the transistor at Bell Labs 1948 – the transistor at Bell Labs 1958 – the integrated circuit 1958 – the integrated circuit 1961 – RTL digital logic 1961 – RTL digital logic 1971 – the microprocessor (4004) 1971 – the microprocessor (4004)

5 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Early programming Countess of Lovelace (1823) wrote programs for the Analytical Engine Countess of Lovelace (1823) wrote programs for the Analytical Engine Machine Language then Assembly Language Machine Language then Assembly Language Grace Hopper (1957) develops FLOW- MATIC Grace Hopper (1957) develops FLOW- MATIC FORTRAN, ALGOL, and RPG FORTRAN, ALGOL, and RPG COBOL COBOL

6 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Modern programming Visual BASIC (most common business) Visual BASIC (most common business) Visual C/C++ (most common technical) Visual C/C++ (most common technical) JAVA (most common web) JAVA (most common web) ADA and PASCAL ADA and PASCAL C# (gaining on web) C# (gaining on web)

7 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Early Microprocessors 4004 the first microprocessor (4-bit) 16K RAM 4004 the first microprocessor (4-bit) 16K RAM 8008 (8-bit) 8008 (8-bit) 8080 (8-bit) 64K RAM, 2Mhz clock 8080 (8-bit) 64K RAM, 2Mhz clock 8086 (16-bit) 1M RAM, 5MHz clock 8086 (16-bit) 1M RAM, 5MHz clock (16-bit) 16M RAM, 16MHz clock (16-bit) 16M RAM, 16MHz clock

8 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e 32-bit Microprocessors 80386, 4G RAM, 33 MHz clock 80386, 4G RAM, 33 MHz clock 80486, 4G RAM, 66 MHz clock 80486, 4G RAM, 66 MHz clock Pentium, 4G RAM, 66 MHz clock Pentium, 4G RAM, 66 MHz clock Pentium Pro, 64G RAM, 133 MHz clock Pentium Pro, 64G RAM, 133 MHz clock Pentium II, 64G RAM, 233 MHz clock Pentium II, 64G RAM, 233 MHz clock Pentium III, 64G RAM, 500 MHz clock Pentium III, 64G RAM, 500 MHz clock Pentium 4, 64G RAM, 1.5 GHz clock Pentium 4, 64G RAM, 1.5 GHz clock

9 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e The P nomenclature P1 – 8086/8088 class P1 – 8086/8088 class P2 – class P2 – class P3 – class P3 – class P4 – class P4 – class P5 – Pentium class P5 – Pentium class P6 – Pentium Pro/Pentium II, Pentium III, and Pentium 4 class P6 – Pentium Pro/Pentium II, Pentium III, and Pentium 4 class

10 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Cache Memory A temporary high speed memory that buffers the slower DRAM from the higher speed microprocessor. A temporary high speed memory that buffers the slower DRAM from the higher speed microprocessor. Usages in bursts of 4 memory-sized chunks of data (today 4, 64-bit numbers) Usages in bursts of 4 memory-sized chunks of data (today 4, 64-bit numbers) Level 1 (small cache for local high-speed storage) Level 1 (small cache for local high-speed storage) Level 2 (larger cache for local high-speed storage. Level 2 (larger cache for local high-speed storage. Level 3 (large cache on Pentium 4 chip) Level 3 (large cache on Pentium 4 chip)

11 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Memory Organization Memory is organized in byte-sized (wide) chunks of data Memory is organized in byte-sized (wide) chunks of data Memory is numbered in bytes Memory is numbered in bytes Memory is number in hexadecimal addresses or locations Memory is number in hexadecimal addresses or locations Modern memory is 64-bits wide containing 8 bytes per memory physical location. Modern memory is 64-bits wide containing 8 bytes per memory physical location. Modern DRAM is SLOW! (40 ns per a random access) Modern DRAM is SLOW! (40 ns per a random access) Buffering and double clock edge transfers can speed memory access times to about 25 MHz Buffering and double clock edge transfers can speed memory access times to about 25 MHz

12 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Microprocessor Internals

13 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Computer Block Diagram

14 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Computer System Functions CPU (microprocessor) – performs CPU (microprocessor) – performs arithmetic and logic operations (table 1-4) arithmetic and logic operations (table 1-4) data transfers (to memory or i/o) data transfers (to memory or i/o) program flow via simple decisions (table 1-5) program flow via simple decisions (table 1-5) Memory – stores program and data Memory – stores program and data I/O – communicates to humans and machines (figure 1-11) I/O – communicates to humans and machines (figure 1-11)

15 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e I/O Space Port 0000H to ffffH (64K 8-bit i/o devices) Port 0000H to ffffH (64K 8-bit i/o devices) Two major sections Two major sections System devices (motherboard, etc) System devices (motherboard, etc) Reserved for expansion Reserved for expansion Various I/O devices that control the system are not directly addressed. System BIOS Rom addresses these devices. Various I/O devices that control the system are not directly addressed. System BIOS Rom addresses these devices. Access made through OS or BIOS function calls to maintain compatibility from one computer system to another Access made through OS or BIOS function calls to maintain compatibility from one computer system to another

16 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e DOS Memory System

17 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Windows Memory Map

18 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e DOS vs. Windows Memory 1M memory system for DOS 1M memory system for DOS 4G memory system for Windows 4G memory system for Windows DOS is a 16-bit system DOS is a 16-bit system Windows is a 32-bit system Windows is a 32-bit system DOS TPA is 640K bytes (figure 1-8, 1-9) DOS TPA is 640K bytes (figure 1-8, 1-9) Windows TPA is 2G bytes (or with a modification to the registry, 3G bytes) Windows TPA is 2G bytes (or with a modification to the registry, 3G bytes)

19 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Computer Structure

20 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Buses Address Bus – selects a location in the memory or a specific I/O device Address Bus – selects a location in the memory or a specific I/O device Data Bus – transfers data between the microprocessor and the memory or I/O Data Bus – transfers data between the microprocessor and the memory or I/O Control Bus – selects I/O or memory and causes a read or a write Control Bus – selects I/O or memory and causes a read or a write See Table 1-6 for Bus widths and memory sizes See Table 1-6 for Bus widths and memory sizes

21 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Reading from Memory Multiple machine cycles are required when reading from memory, because it responds much more slowly than the CPU. The steps are: Multiple machine cycles are required when reading from memory, because it responds much more slowly than the CPU. The steps are: address placed on address bus address placed on address bus Read Line (RD) set low Read Line (RD) set low CPU waits one cycle for memory to respond CPU waits one cycle for memory to respond Read Line (RD) goes to 1, indicating that the data is on the data bus Read Line (RD) goes to 1, indicating that the data is on the data bus

22 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Memory Organization 8086/8088 – 8- or 16-bits in width 8086/8088 – 8- or 16-bits in width – 16-bits in width – 16-bits in width 80386/80486 – 32-bits in width 80386/80486 – 32-bits in width Pentium/Pentium 4 – 64-bits in width Pentium/Pentium 4 – 64-bits in width

23 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e 8-bit Data

24 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e 8-bit Data Formats In the assembler use: In the assembler use: DATA1 DB 10H In C++ In C++ char Data1 = 0x10; or unsigned char Data2 = 3;

25 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e 16-bit Data

26 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e 16-bit Data Formats In the assembler In the assembler Data3 DW 1000H In C++ In C++ short Data3 = 0x1000; or _int16 Data4 = 23; or unsigned short Data5 = 4;

27 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e 32-bit Data

28 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e 32-bit Data Formats In the assembler In the assembler DATA6 DD H In C++ In C++ int Data6 = 0x ; or unsigned int Data7 = 34566; or UINT Data8 = 344;

29 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Floating-point Data

30 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Floating-Point Formats In the assembler In the assembler DATAA DD 23.4 DATAB DQ DATAR DQ 3.5E2 In C++ In C++ float DataC = 23.4; double DataD = -345; double DataE = 3.5e2;

31 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Conversions Conversion to a number base requires learning exactly what the waits of each position are worth. Conversion to a number base requires learning exactly what the waits of each position are worth. Once the weights are learned, conversion is a simple task that can even be accomplished on a calculator. Once the weights are learned, conversion is a simple task that can even be accomplished on a calculator. To convert a decimal integer to any radix divide by the radix and keep the remainders as significant digits in the result To convert a decimal integer to any radix divide by the radix and keep the remainders as significant digits in the result

32 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Conversions (continued) To convert a fraction to any radix multiply by the radix and keep the whole number part of each result To convert a fraction to any radix multiply by the radix and keep the whole number part of each result

33 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Complements Twos complements are used to store negative data in modern computers Twos complements are used to store negative data in modern computers To twos complement a number invert all the bits and ten add 1 to the result To twos complement a number invert all the bits and ten add 1 to the result

34 © 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Hexadecimal-coded Binary Binary numbers are often coded in groups of 4 bits to represent hexadecimal numbers. Binary numbers are often coded in groups of 4 bits to represent hexadecimal numbers = 41A = 41A 16 3C45 16 = C45 16 =


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