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Overview of Popular DSP Architectures: TI, ADI, Motorola R.C. Maher ECEN4002/5002 DSP Laboratory Spring 2003

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ECEN4002 Spring 2003Other DSP Architectures R. C. Maher2 Introduction Most DSP microprocessor architectures share the common features: fast MAC with guard bits, Harvard architecture, and parallel compute/moves Alternatives have to do with number and size of registers, on-chip memory, variety of instructions, and pipelining Most common DSP architectures have “legacy baggage:” new designs must be compatible with older designs to allow code re-use

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ECEN4002 Spring 2003Other DSP Architectures R. C. Maher3 Motorola 563xx As we know from the lab assignments, the Motorola 563xx has the following characteristics: –24-bit word size, dual 56-bit accumulators –X,Y,P data buses –8 DAG registers (linear, modulo, reverse) –4 general registers –Integrated MAC/ALU (no parallel computation)

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ECEN4002 Spring 2003Other DSP Architectures R. C. Maher4 “Old” TI TMS320 The Texas Instruments TMS320 family appeared in the early 1980s –16-bit word size, single 32-bit accumulator –D,P data buses –5 aux registers (data or address) –No modulo support –Integrated MAC/ALU (no parallel computation)

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ECEN4002 Spring 2003Other DSP Architectures R. C. Maher5 Example TMS320 Code LAC XN,15 * load accumulator with shift LT D1NM1 * load T register with state MPY A11 * multiply with coef LTA D1NM2 * load T with next state MPY A21 * multiply with coef APAC * accumulate product SACH D1N,1 * store result with shift

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ECEN4002 Spring 2003Other DSP Architectures R. C. Maher6 “New” TI C54x –16-bit word size, 17x17 multiply, dual 40-bit accumulators –1 Prog, 3 Data, 4 Address buses –8 auxiliary registers (linear, modulo, reverse) –Integrated MAC/ALU (no parallel computation) TI also makes floating point ‘C30 and C6x parts

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ECEN4002 Spring 2003Other DSP Architectures R. C. Maher7 “Old” ADI 21xx Analog Devices original DSP family was organized as follows: –16-bit word size, single 40-bit accumulator –D,P data buses (16-bit data, 24-bit program) –10 general purpose registers –Dual 4-register DAGs (similar to 563xx) –Separate ALU, MAC, and SHIFT (for parallel computation) –“Shadow” registers for fast context switching

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ECEN4002 Spring 2003Other DSP Architectures R. C. Maher8 ADI Assembly Language Motorola and TI use a register transfer assembly language format Move x0,y0 Add x0,b Mac x0,y0,a ADI uses an algebraic assembly language AX0 = MR1 AR=AX0+AY0 MR=MR+MX0*MY0

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ECEN4002 Spring 2003Other DSP Architectures R. C. Maher9 ADI Floating point “Sharc” ADI Sharc (super Harvard architecture) –16 40-bit GP registers –32-bit or 40-bit IEEE floating point representation, and fixed point math, too –D,P buses –Dual DAGs

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ECEN4002 Spring 2003Other DSP Architectures R. C. Maher10 “New” ADI/Intel Blackfin Dual 16-bit MACs, 2 40-bit ALUs, 4 8-bit “video” ALUs Dual DAGs, which include base, length, and offset registers (no “power-of-two” alignment) 8 GP registers Many flexible parallel operations on various data types/lengths

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ECEN4002 Spring 2003Other DSP Architectures R. C. Maher11 DSP-like Features for GP micros DSP algorithms often fit a “single instruction, multiple data” (SIMD) framework Intel, AMD, and Motorola have DSP-like instruction extensions on their processors (MMX, SSE, 3D-NOW, Altivec, etc.) Most of these do not support a true MAC with guard bits

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ECEN4002 Spring 2003Other DSP Architectures R. C. Maher12 Conclusion DSP design has evolved to include parallel computation hardware, flexible addressing, and more processor registers Common embedded system designs now have a general purpose processor coupled with a DSP core Compilers for DSPs are still evolving: usually compile the code, profile it, then hand code inner loops and “hot spots”

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