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Technology & Architecture

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1 Technology & Architecture
CoolRunner™-II Technology & Architecture Welcome to the CoolRunner-II Quick Start. Before we get into the applications, we will give a short overview of Xilinx’ CoolRunner-II CPLD family CoolRunner-II Technical Pitch

2 Introducing CoolRunner-II
0.18 process technology System voltage integration Advanced design features Multiple I/O standards and I/O banks Input hysteresis Extra clocking modes Architecture allows design flexibility Ultra low power using RealDigital technology Allows CoolRunner full-CMOS circuitry to run at extremely low power without compromising performance The process is very similar to that of our FPGA products, with an added on nonvolatile module. Key to the FZP™ approach is that the NV cells are not in the speed path. Depending on the density of the part, metal layers are included to maximize speed, minimize power and area. The I/Os operate down to 1.5V and up to 3.3V. Key to the architecture is to serve both the high speed, mainstream CPLD markets (datacom, computing, telecom) as well as portable markets (MP3, PDA, SmartCard I-face, etc.) Densities range from 32 up to 512 macrocells CoolRunner-II Technical Pitch

3 High Level Architecture
Clock and Control Signals Function Block 1 Function Block n MC1 MC1 I/O MC2 16 FB 16 FB MC2 I/O I/O I/O PLA 16 PLA 16 I/O Blocks I/O Blocks AIM 40 40 Very traditional architecture incorporating PAL-like function blocks interconnected with the Advanced Interconnect Matrix (AIM). Note the boundary scan/ISP controller delivers the usual in system programming, but all density parts will program in one second or less. All charge pump circuitry is contained on chip. The number of function blocks will depend on the density/size of the device. For instance the 32 macrocell CoolRunner-II will have 2 function blocks, while the 384 macrocell CPLD will have 24 function blocks. The largest part is 512 macrocells. I/O I/O MC16 MC16 16 Direct Inputs Direct Inputs 16 CoolRunner-II Technical Pitch

4 Function Block 16 macrocells available
40 true and complement input signals from AIM Global signals available at macrocell Product terms add more clocks, OEs, S/Rs Product term sharing allows very high fit rate PLA architecture features excellent pinlocking The Function Block has 40 inputs (signals and complements) into 56 product terms which are shared by 16 macrocells. The product term distribution structure is a PLA, which permits attachment of product terms to any macrocell within the FB with identical and fast time delays. Note that product terms can be freely shared. Abundant product terms based control signals (set, reset, oe, clk) as well as FB level - “control” terms are included to supplement the global signals. The resulting architecture has a very high fit rate and retains pinout through multiple design iterations. CoolRunner-II Technical Pitch

5 Function Block Architecture
40 From AIM MC 1 Feedback to AIM PLA Array 40x56 To I/O Block 16 56 Product Terms The PLA array has 40 input signals from the AIM. The signals are then inverted in the function block in order to have true and complement values available. The PLA is 40x 56 terms wide. The product terms are not dedicated to a particular macrocell, but shared within the function block. The available 56 product terms can be used for data and control functions, including clocking, reset, set, and output enables. Each function block has 16 macrocells. All global set, reset, and clock signals are available at each macrocell. The output from the macrocell goes both directly to the I/O block as well as feedback to the AIM for use in other logic. MC 16 3 Global Set/Reset Global Clocks CoolRunner-II Technical Pitch

6 Macrocell Architecture
FB Inputs from AIM application notes: 40 PLA Array 49 P terms Macrocell 4 Control Terms from I/O Block (Direct Input) Feedback to AIM PTA PTA CTS GSR GND PTB VCC PTC GND to I/O S D/T Q Here is the basic building block. All macrocells are the same with the exception that buried macrocells do not go to an I/O. Note the PLA structure (upper left) delivering up to 56 p-terms to a given site. The muxes are programmed to select as needed by the design software. The flop can be configured with D,T or latch capability. Clock polarity can be selected per macrocell. Clocks can be attached directly, or locally doubled. More on this later. FIF Latch DualEDGE PTA,B,C CTS CTR CTC = programmable cell = product term signals = control term set = control term reset = control term clock 3 GCK PTC CE CK CTC R PTC PTA CTR GSR GND CoolRunner-II Technical Pitch

7 I/O Block Characteristics
VREF for Local Bank HSTL & SSTL VCCIO VREF to AIM I/O Pin 128 macrocell and larger devices to Macrocell (Direct Input) Input Hysteresis 3.3V - 1.5V Input Weak Pullup/Bus Hold Slewrate VCCIO from Macrocell I/O Pin The I/O block is responsible for multiplexing between the output buffer and data entering the CPLD via the pin. The I/O block can be configured as an input, output, or both. The output enable mux is software selectable with the OE option including: enabled, disabled, product term B, control term, open drain, CGND, or one of 4 global OE signals. The input structure in CoolRunner-II allows several options to the designer. The input can be configured to have hysteresis, if selected, for noisy or slow edge rate signals. Each pin can be individually configured to have hysteresis or not. This improves noise margin at very low logic signal levels and improves the ability to make clocks with minimal external circuitry (maybe on the clocks). Or the I/O block can read an SSTL or HSTL input signal. The SSTL and HSTL standard is available on the 128 macrocell and larger densities. For the required VREF in SSTL and HSTL standards, a additional pin must be dedicated to providing the reference voltage. A pin when dedicated to this function drive the VREF bus throughout the entire I/O bank. A VREF pin must be specified of each I/O bank. The inputs can come in and directly attach to the D input of the flip flop to act as a direct input register or feed into the AIM array. The I/Os are configured to range across multiple 3.3V to 1.5V I/O standards. Enabled Control Term PTB 4 / GTS[0:3] CGND Open Drain Disabled CoolRunner-II Technical Pitch

8 Note: 128 MC device estimate
Reducing Power Icc = C x V x f + Iddq To reduce power: Lower capacitance Lower voltage Lower frequency 0.18 m lowers capacitance Low 1.8V How can we reduce the frequency? ~ 200mA Traditional Sense Amp Designs 1.8 Volt (est) 2.5 Volt Icc 3.3 Volt Standard CMOS ICC equation. Note the curve on the bottom shows this behavior, but it fails to tell you how to get to zero. To take a CMOS product to zero, you basically have to stop the inputs from switching. This isn’t easy! By transitioning CoolRunner-II to 0.18 micron process, capacitance is lowered as well as operating voltage. Vcc can be 1.8V. So how else does CoolRunner-II lower power. 1) by implementing the CoolRunner patented chain of gates structure known as FZP. 2) by allowing customers to lower frequency (using clock divider and CoolCLOCK) One feature that is really important: Note how sense amp CPLDs increase in quiescent current when the voltage drops. So even if you are decreasing voltage, the power does not decrease in a linear fashion. CoolRunner devices provide an additional power savings in that the current consumption also decreases. Only the Fast Zero Power technology allows this! ~ 100mA Frequency ~ 200MHz Note: 128 MC device estimate CoolRunner-II Technical Pitch

9 Clock Division Gives solid clock division without using macrocells
Global Clock (GCK2) External Sync Reset Clock Divide By 2,4,6,…,16 DIV2 DIV4 DIV16 to FB 1 to FB n Divide Select Gives solid clock division without using macrocells Duty cycle improvement Available in larger densities (128 macrocells and above) One way to reduce switching inputs is to slow down clocks. They tend to be the fastest switching signals, anyway. CoolRunner-II provides the ability to divide global CLK2 by 2,4,6,8,10,12,14,16 as standard settings. Other values can be obtained using the macrocells. One clock divider is included to: provide slower clocks without additional circuitry add in a synchronous reset condition to avoid runt clocks pulses The clock divider is an optional feature, which is set in the programming file. All GCK pins attach to standard I/O pins, so if you don’t need a GCK, you can still use it as a standard I/O. Note the resulting output of the clock divider will have 50% duty cycle. The clock divider circuit will actually improve a poor duty cycle on an incoming clock. CoolRunner-II Technical Pitch

10 DualEDGE Flip Flops Advantages:
D/T/L Q to I/O D T FF Latch DualEDGE 3 GCK PTC CE CLK CT PTC Advantages: Distribute divided clock globally then double locally at macrocell Decrease Icc on global clock nets Use 2x clocking for double data rate (DDR) applications No additional insertion delay This is a macrocell level feature. Each macrocell has the ability to clock on both edges of an input clock. The software allows the user to set simple switches to dictate the use the clock doubler. To reduce ICC, you can deliver a clock at half the frequency, drive the clock net at half frequency, then double it locally. This lowers consumed power by switching lower on nets that tend to have high capacitance. In order to be able to run this at highest bandwidths, users should be aware that clocks should have as close as 50% duty cycle as possible. Other uses of this could serve as a way to “square up” duty cycle by using the clock divider on the input clock, then using the clock multiplier to recover the original clock. CoolRunner-II Technical Pitch

11 CoolCLOCK Device Routing Input Clock Divide Macrocell 
MC Clock Inputs D/T/L Q D T Latch DIV2 DualEDGE GCK2 Global Divided Clock Divide by 2 Sync Reset CoolCLOCK is the term used to cascade the clock divider with the clock doubler. Externally, a clock of ‘F’ frequency can be delivered into the device. Drop it onto the GCK2 clock divider, and dictate use of the clock double later at the macrocell and get the benefits of divide by 2 and multiply by 2. Note the externally delivered clock does not need 50% duty cycle here as the clock divider takes care of it for you unless you are approaching the upper bandwidth of the clocking capability of the part. The CoolCLOCK feature of CoolRunner-II reduces ICC. CoolCLOCK allows you to deliver a clock at half the frequency, drive the clock net at half frequency, then double it locally. This lowers consumed power by switching lower on nets that tend to have high capacitance. Another dimension of power savings for the CoolRunner-II CPLD! CoolRunner-II Technical Pitch

12 DataGATE Available on all input pins (except JTAG pins)
Data Latch to AIM DataGATE Assertion Rail Input Pin Configuration Bit Available on all input pins (except JTAG pins) Available for all I/O types Selectable on a per pin basis Data latch holds last valid pin value DataGATE allows additional power savings Can be used to disable active board inputs DataGATE can be also used for debugging and Hot Plug Input Suppose you have a set of signals that are used infrequently - say, only at initialization time. You could basically take that set of signals and switch off their influence on the CPLD - under design control. Another example might be a CPLD that resides on a data bus. Most of the time the data on the bus is not intended for the CPLD, but the signals are switching a good deal of the circuitry internal to the part. DataGate is built by inserting pass transistor logic into the input cells under the control of an internally distributed control or “assertion” rail. One macrocell drives the rail. Any logic you want can be on the input of the macrocell - a simple input pin from an off chip system power controller, a state machine, or timer that toggles that macrocell. When it asserts, any inputs that are attached (your choice of any, some or all) will be blocked until the rail is released. You don’t have to use it, but it is another way you can further reduce your power. Each input pin can be optionally selected to participate or not. Automatic circuitry will hold the last state when the rail asserted. Upon releasing the rail, the internal pin value will be the same as it was. If you wanted to, all (but one) input could be attached letting you get very close to the origin of the ICC vs frequency curve. No external circuitry needed. CoolRunner-II Technical Pitch

13 500mV Input Hysteresis Supports simple oscillation schemes
Ideal for slow edge rate, noisy signals Analog comparators & sensors Hall effect switches IR inputs R/C oscillators Eliminate external Schmitt trigger buffers Reduces power consumption with slow signals CoolRunner-II + _ In V All CoolRunner-II input pins have an input hysteresis option. Input hysteresis interprets slow edge, noisy signals avoiding any glitches that may normally be read by the input. Input hysteresis will facilitate the creation of oscillators that are R/C based. These types of oscillators typically have very slow rise and fall times, and would either not function with standard inputs, or cause a large amount of power consumption. This type of input allows for simple interfacing to analog signals, whether using the input as a clock or as a signal. Handheld designs are almost always tight on PCB space. Input hysteresis provides designers with a tool to minimize external components. Whether using the inputs to create a clock, or reducing the need for external buffers to sharpen up an input signal, the new CoolRunner-II CPLD inputs provide designers with a flexible and powerful feature. CoolRunner-II Technical Pitch

14 I/O Performance & Flexibility
XC2C32 XC2C64 XC2C128 XC2C256 XC2C384 XC2C512 I/O Banks 1 2 4 LVTTL 33 LVCMOS 33, 25, 18, 15* SSTL3_I, SSTL2_I, HSTL_I Input Hysteresis Option Slew Rate Control CoolCLOCK DataGATE DualEDGE flip flop Clock Divider Bus Hold output Hot Pluggable This is the planned CoolRunner-II line-up. 32 to 512 macrocells with up to 3.0ns tPD performance. Note the uniform delivery of features, where only the smallest parts omit the memory standards, CoolClock and DataGate. * 1.5V inputs need hysteresis CoolRunner-II Technical Pitch

15 CoolRunner-II Applications
Ideal for high speed designs: High performance CPLD Advanced features Voltage translation for “free” Double data rates Target device for portable designs: Lowest power Maximum battery life Lower heat dissipation Small packaging Chip scale packaging Classic applications are the targets here - both high speed and portable. Typically, high speed is plugged into the wall and portable is powered by a battery(ies). CoolRunner-II Technical Pitch

16 CoolRunner-II Family Overview
This is the current CoolRunner-II line-up. 32 through 512 macrocells with performance up to 3.5ns TPD, 333MHz FSYSTEM , 454MHz FTOGGLE , up to four I/O banks and 1.5 to 3.3 volt I/O standards. Advanced features include DualEDGE Flip Flops, clock divide, CoolCLOCK, DataGATE, 500mV input hysteresis. Also note the wide choice of package options to meet every need from the smallest chip scale packages available for portable applications to high I/O count BGA packages for higher performance applications . * Note: T speeds are preliminary and 1.5V inputs need hysteresis P D CoolRunner-II Technical Pitch

17 CPLD Software CoolRunner-II Software support
ISE WebPACK 5.2i WebFITTER Full feature support All Xilinx CPLDs supported! CoolRunner-II CoolRunner XPLA3 XC9500/XL/XV CoolRunner-II Technical Pitch

18 IQ Solutions Multiple facets
Programmable products IP cores System solution boards PLD family members available in the range of -40°C to +125 C : Design services eSP web portal Customer education Device Type Spartan XL XC9500 & XL CoolRunner XPLA3 Spartan-II CoolRunner-II Spartan-IIE XCS05XL, XCS10XL, XCS20XL, XCS30XL, XCS40XL XC9536XL, XC9572XL XCR3032XL, XCR3064XL, XCR3128XL, XCR3256XL, XCR3384XL, XCR3512XL XC2S15, XC2S30, XC2S50, XC2S100, XC2S150, XC2S200 Q1CY03 FPGAs temperature is junction CPLDs temperature is ambient CoolRunner-II Technical Pitch

19 CoolRunner-II Technology Summary
Silicon performance of Xilinx FPGAs with the single-chip integration of CPLDs Architecture combines 9500-style macrocell with XPLA3’s PLA for best silicon/software efficiency Industry leadership in: High performance I/O standards Clock management capability Low-power features Uncompromised performance at 1.8 volts

20 Appendix CoolRunner-II Technical Pitch

21 RealDigital Design Advantage
Turbo vs Non Turbo Larger R = slower response & less power RealDigital : CMOS Everywhere - Zero Static Power C B A D Vcc A B C Sense amplifier 0.25mA each - Standby Higher ICC at Fmax Traditional CPLDs - bipolar sense amp product terms Always consumes power Even at standby Performance is traded for power consumption as devices get larger CoolRunner-II RealDigital design uses 100% CMOS for product terms Virtually no standby current Combines high performance & ultra low power No power limits on device size CoolRunner-II Technical Pitch

22 Common logic may be shared in CoolRunner-II
Logic Optimization PAL: Requires 4 pt’s! PLA: Requires only 3 pt’s! A B C A B C In order to understand the flexibility of the PLA array, it is helpful to understand the differences between a PAL and a PLA. The main differentiating factor between a PAL and PLA product term structure is the ability to share product terms. The PLA structure is made up of a programmable AND array followed by a fixed OR array. Product terms are dedicated to specific OR functions and can not be shared. This means that expressions with common elements (like the equations in blue) require that the common product term (A & B) must be duplicated. In order to satisfy both of these equations, a total of four product terms must be used. The PAL array can not share common logic and implementation of logic requires more product terms. The PLA structure has a programmable OR array. The PLA structure allows common and popular product terms to be used in multiple OR terms. The figure on the right for instance, creates a single product term for A and B. This product term can then be shared in both OR terms to create A & B # C and A & B # !C. The PLA structure in this case actually saved one product term. CoolRunner-II implements the PLA product terms structure to allow product term sharing, thus improving a CPLD fit and facilitating flexible pin locking (by saving logic in a function block). Can NOT share common logic X = A & B # C Y = A & B # !C X Y X Y Indicates ‘used’ junction Common logic may be shared in CoolRunner-II Indicates ‘unused’ junction Indicates ‘fixed’ junction CoolRunner-II Technical Pitch

23 DDR SDRAM Interface DualEDGE facilitates DDR Utilizes SSTL interface
Address Data Control DDR SDRAM P DualEDGE facilitates DDR Utilizes SSTL interface This is intentionally simplistic just showing the usual usage of a CPLD to be the memory interface. Usually, it initializes the internal memory variables, then muxes address and data while delivering precisely timed strobes for read and write into the memory chips. CoolRunner-II Technical Pitch

24 System Voltage Integration
CoolRunner-II features flexible I/O banking 1.5V P 1.8V I/O 3.3V SRAM 2.5V Flash Some customers never really use the logic inside. They basically use the parts as a voltage clearing house to permit interfacing across different voltage formats. Critical here is simply getting the voltage right and being fast enough to not skew the signals to 5 nanoseconds TPD is usually fast enough. CoolRunner-II Technical Pitch

25 PDA Battery Compact Flash Flash SRAM LED P Docking Cradle LCD Keypad
SMBus Battery Compact Flash Flash SRAM IrDA LED P UART Docking Cradle LCD SPI DragonBall or StrongArm, today’s PDAs have a lot in common. All need memory and EPROM for the basic PIM. Also, there is an interactive LCD interface and more are adding in external busing to permit add-on goodies- like cameras, GPS units, telephones, b interfaces and so-forth. CoolRunner-II handles them all. Keypad Touchscreen CoolRunner-II Technical Pitch

26 Web Tablet SPI PWM HIB SMBus ISA Bus Smart Battery Tablet ID ADC RF
Module SDRAM High End Processor LCD Panel Touch Screen Compact Flash/ Expansion HIB PWM ISA Bus SPI SMBus Interfacing the system chips to the processor includes interfacing the RF chips. Today, this can also include creating I2C and SPI (solutions on the web) along with CF-II and PCMCIA interfaces (in the works). Lots of wireless goodies and cell phones currently being handled by our XPLA3 parts will easily migrate to CR-II to get even greater power savings. Battery life is the key to this market. CoolRunner-II Technical Pitch

27 Low Power Clock Divide Input signals: global clock (GCK2) & external sync reset Control bits: enable/disable, & delay bit Divide by n (2, 4, 6, 8, 10, 12, 14, or 16) Clock Cycles 1st 3rd 5th 7th 9th 17th Global CLK2 Sync Reset Divide by 2 Delay bit = 0 (No delay) Besides the two input control signals for the clock divider, global clock (GCK2) and the external synchronous reset, two other configuration bits are needed. The first control bit enables or disables the clock divider feature. The second control bit allows the designer to delay the divided clock pulse one full cycle after the reset is de-asserted. The top two waveforms for Divide by 2 and Divide by 16 show the timing diagram when the delay bit is set to 0 or no delay. The bottom two waveforms for Divide by 2 and Divide by 16 show the timing when the delay is enabled or the delay bit is set to 1. Note the delay of the divided clock output is ONE full cycle. This allows designers to take advantage of the DataGate feature on inputs and allow for any startup propagation delays. Both of these control bits are set by the user when synthesizing the design. Note that divide by 2, 4, 6, 8, 10, 12, 14, and 16 are available. Divide by 16 Divide by 2 Delay bit = 1 (Delay enabled) Divide by 16 CoolRunner-II Technical Pitch

28 Twice the performance of the system clock with double data rate
DualEDGE Performance Without DualEDGE 1st External CLK 2nd 3rd 4th 5th Din Output Clock Cycles Internal Clock Doubler With DualEDGE This slide simply illustrates how to use the DualEDGE Flip Flops to achieve double data rates. The purple label for Din and Output represents a single data rate output. The green label at the bottom of the diagram shows the output changing at 2x the previous output data rate. DualEDGE allows previous output data to reach 2x levels. Twice the performance of the system clock with double data rate CoolRunner-II Technical Pitch

29 ODD CLOCKS with DualEDGE and CLOCK Divider
Clock Divider gives ÷ 2,4,6,8,10,12,14,16 Dual EDGE double response ODD CLOCKS at DualEDGE Flip Flops ÷ ÷ 14 x 2 ÷ ÷ 10 x 2 ÷ ÷ 6 x 2 CoolRunner-II Technical Pitch

30 Multiple CLOCKS with One Global net
Example: pin ÷ 8 distributes to Global Net Some flops accept CLOCK, respond to ÷ 8 Some DualEDGE Flip Flops respond to ÷ 4 CoolRunner-II Technical Pitch

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