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1 JAZiO ™ Incorporated Incorporatedwww.JAZiO.com Digital Signal Switching Technology.

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Presentation on theme: "1 JAZiO ™ Incorporated Incorporatedwww.JAZiO.com Digital Signal Switching Technology."— Presentation transcript:

1 1 JAZiO ™ Incorporated Incorporatedwww.JAZiO.com Digital Signal Switching Technology

2 2 What Is JAZiO? A small company in San Jose, CA specializing in Intellectual Property An I/O technology useful for transmitting data between semiconductor chips

3 3 JAZiO Technology Innovative I/O switching technology Can be used to achieve >2 Gigabits/sec/pin with current semi and packaging technology Has built in timing Can use slow edges which take the whole bit time Detects data value as soon as transition occurs Uses differential sensing with low signal levels Yet uses only 1 pin per data signal

4 4 Why Is JAZiO Needed? Internal/External Gap Gap Is Growing!!! Processor Bus

5 5 Conventional (Older) Technology  Receiver Has No Precision  Too Slow for High Performance Products Receiving ChipDriving Chip DR Trace

6 6 Differential Technology  Precise Receiver  But Requires Two Pins Per Data Bit Receiving ChipDriving Chip D R Traces D True Comp

7 7 Pseudo-Differential Technology  Static V REF  A Compromise Receiving Chip Driving Chip D R Trace V REF

8 8 Full Differential vs Pseudo Differential Differential develops very quickly and is symmetric around the DC bias of the receiver R True Comp Full Differential R Data V REF Pseudo Differential Differential develops slowly and is not symmetric around the DC bias of the receiver Differential Achieves Higher Data Rates Per Pin Detecting “0” or “1” True Comp Bit Time Detecting “1” Data V REF Detecting “0” Bit Time

9 9 Problems with Differential Requires two, logically redundant, pins per bit To achieve a net data rate of, say, 2 Gigabits/sec/pin, each pin must switch at 4 Gigabits/sec The driver, the package, the PCB trace, the tester all must deal with the 4 Gigabits/sec PCB attenuation of signals increase with frequency (Dielectric absorption) or sqrt(f) (Skin effect) Differential will “hit the wall” due to signal attenuation and reach the end of its scalability while JAZiO continues to scale

10 10 JAZiO JAZiO was founded in order to allow differential sensing with one pin per bit 1.Therefore data rates comparable to differential technology can be achieved with half the pins 2.Or twice the data rate can be achieved with the same number of pins But no pins need to switch faster than the data rate

11 11 JAZiO Technology  Single Data Pin Per Bit  Three Input Receivers Receiving Chip Driving Chip D R Traces D D D R Data1 DataN Voltage/Timing References (VTR) True Comp

12 12 Differential Sensing with One Pin Per Bit In full differential systems: –Some signals go high and each has a complement going low –Some signals go low and each has a complement going high JAZiO provides: –One VTR signal to stand in for all the complements going low –A complement VTR to stand in for all the complements going high

13 13 16 Bits of Full Differential VTRs are Voltage and Timing References VTR R D0 VTR R D15 CLK R D0 R D15 16 Bits of JAZiO 34 High Speed Pins18 High Speed Pins

14 14 JAZiO Solution Steering Logic Data Output VTR Data Input VTR B A Dual Comparators are used In cases 1 and 6 Comparator A makes a differential comparison In cases 2 and 5 Comparator B makes a differential comparison In the other four cases Data Input does not change Data is driven coincidentally with Voltage/Timing References Data Input VTR One Bit Time Provide alternating Voltage/Timing References switching at the data rate Next Bit Time 8 different combinations of VTR and Data Input

15 15 Steering Logic The trick is to know how to select between Comparators A and B and what to do when Data Input does not change

16 16 Steering Logic Generate Steering Logic signals (SL and SL) Use them with Data Output from previous Bit Time to select between Comparators A and B Also use them for data latching SL Receiver Output XOR in out XOR in out Data Input VTR A B Latching System Latched Output

17 17 Data Output SL Initialization or Receiver Enable SL VTR Data Input Data Input XOR 55 Small Transistors Per Bit No PLL/DLL Required No die size penalty!!!

18 18 The receiver cell is: 22um x 55um (Including routing channels) The pad cell is: 70um x 80um

19 19 Time Domain Decision is made in the Time Domain rather voltage domain VTR Data Input First Look for change Determine no- change and switch to Comparator B  0.5V SL Data Output XOR in out XOR in out Data Input VTR A B

20 20 JAZiO ™ Receiver Operation A SL XOR-B Data Output in out Data Input VTR B XOR-A The No-change Cases Initialize Data Input Data Output VTR SL CompA CompB XOR-B XOR-A

21 21 vtr Data Input xnora Xnorb Data Output Time (nS) Voltage (V) 4nH Package Break-Before-MakeBreak-And-Remake

22 22 Data Skew at Receiver Simulations show that width of Skew Band can be up to 40% of bit time VTR Data Input  500mV + 100mV - 150mV Recommended Skew band 1.25V/ns Bit time = 0.5ns

23 23 XORs Provide Receiver Monitor SL Initialization or Receiver Enable VTR Data Input Data Input Data Output SL XNORA XNORB Receiver Monitor MON A MON B

24 24 XORA XORB=Low Break & Remake Break & Remake VTR & Data Marginally Aligned XORB XORA False Select VTR & Data Poorly Aligned XORA=High XORB=Low VTR & Data Well Aligned XOR Waveforms with Alternating Data Pattern Monitoring Alignment

25 25 Advanced Aligning Techniques Monitors provide information on alignment between Data and VTRs Simple means for analyzing interface margins at operating frequency Monitor information can be fed back to Programmable Delays to improve alignment and can also be used for at speed testing Driver Programmable Delay JAZiO Receiver Latch One Data Bit Drivers Programmable Delay SL Generator VTR, VTR- MONB MONA Driving Chip Receiving Chip

26 26 4 Bit JAZiO Receiver From Test Chip

27 27 16 JAZiO ™ Receivers From Test Chip

28 28 Package & ESD Model Low Pass Filter 0.6pf 2nH 0.24  Lead frame 0.6pf 2nH 0.2  Bond Wire 1pf N-Ch Clamp P-Ch Clamp 0.1pf Pad 0.1pf 200  C int To Receiver Input Protection Resistor

29 29 Simulation at 2Gb/s Middle of transmission line Package inductance 2nH Data Output VTR Data Input Time (nS) Voltage (V) Data Output VTR Data Input Time (nS) Voltage (V) At Pin At Receiver Input

30 30 Applying JAZiO Technology JAZiO is the physical I/O layer only –JAZiO provides no protocol –Works with any protocol –Like good tires make any car better Easy to use –No die size penalty –No PLL/DLL or special semiconductor technology –Low Power Can be used anywhere that fast switching, low power, and pin efficiency is useful

31 31 How Can JAZiO Be Used? JAZiO is “essentially” an Open Standard All technology is publicly visible w/o NDA Anyone can see it, study it, simulate it, design it in, build test chips, build prototypes and license before selling products Users can develop their own enhancements around JAZiO technology Patents have been issued and are ready for licensing

32 32 Summary Achieves high performance, low power, high robustness JAZiO requires no die size penalty and saves package cost JAZiO is available to everyone at low cost and applies to any application


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