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Digital Design Elec 290 Study guide for students using Digital Design Principles and Practices, 4 th Ed. by John F. Wakerly Version 9/24/2014 5:48pm

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Lecture Overview Introduction Number Systems and Codes Digital Circuits Combinational Logic Design Principles Combinational Logic Design Practices Sequential Logic Design Principles Sequential Logic Design Practices Memory, CPLDs, and FPGAs

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Lab Overview CADET Breadboard Basic Logic Gates—AND/OR/NOT Introduction to Quartus Software—GUI Introduction to Combinational Logic—Block Symbol Parity Bit Generator/Receivers I/O using Parity Bit Generators Black Box Design—Truth Table Megafunctions—Decoder Adders—flip flops 7-Segment Displays—I/O Counters— Sequential/Asynchronous Accumulators—Synchronous State Machines—Control

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Chapter 1—Introduction Digital vs Analog Digital devices Hardware for Digital Design Software for Digital Design Integrated Circuits Programmable Logic Devices ASICs Printed Circuit Boards (PCBs) Chapter homework: 1.3, Name three advantages of digital logic. Slides seen during this week were from Tocci’s Chapter 1 power point presentation, 45 slides covering history of digital devices vs analog and intro to binary numbers.

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Sample explanations used during lecture 1.Formula for largest number in N bit word 2.Value for binary word 11111111= 255 3.MSB and LSB storage & data communications wiring issues (big/little endian) for bits connected to bus

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Sample explanations used during lecture 1.Sample solution binary to decimal…sum bit weights! 2.Clocking and symbols 1/0 3.Time constant delay vs. frequency 4.Trending reading of rising/falling = faster clocking 5.Quick way to read binary numbers, learning 0-7 (000- 111).

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Chapter 2—Number Systems and Codes Positional Number Systems Hexadecimal and Binary Number systems Conversion of Numbering Systems Addition using Numbering Systems Subtraction using Numbering Systems Ones’ and Two’s Complements Binary Multiplication/Division Codes—Gray, ASCII Error Detection and Correction Chapter homework: Do all questions in the Drill Problems

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White board photos of number conversions I Binary to Decimal showing “weights”Some representative nibbles to have memorized to speed conversions

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White board photos of number conversions II How to convert Decimal # to a binary number Introduction to the Hex numbering system & shortcuts

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White board photos of number conversion III On the left conversion map of hexadecimal to decimal while on the right is Binary Coded Decimal example.

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More photos of number conversions IV Close up of MSD and positions of bits; on left is summary photo with conversion of name to ASCII code

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Chapter 3—Digital Circuits Logic Signals Basic Logic Gates CMOS Logic Bipolar Logic Pull-up resistors Open-drain connections Chapter 3 homework Part 1: 1,5,6,9,10,12,1619, and 23 Drill problems Chapter 3 homework Part 2: 24,26, 33,38,41

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White board photos of logic gates I On the left is the last lecture from Ch2 on polarity. To the right is the opening lecture notes for logic gates & Truth tables.

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Images from lecture in Ch 3 How the ordering of combination circuits makes a difference in the output’s X & Y How the placement of the NOT gate affects the outputs

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More Images from lecture in Chapter 3 Example of timing diagram showing inputs and outputs

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More images from lecture in Chapter 3 Using Excel to solve logic circuits Circuit that was used for Excel example, Fig 3-15b, page 78Spreadsheet example demonstrating Excel logic functions used for truth table construction and solution.

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More Chapter 3 board work Expounding on Truth Table for Figure 3-15 (a) and another Explanation of what happens when you use output to sink LED current and how to calculate current protection resistor.

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Chapter 4—Combinational Logic Design Principles Boolean Algebra Duality Combinational Circuit Analysis Combinational Circuit Synthesis Combinational Circuit Reduction/Simplification K-maps Sum of Products Product of Sums Chapter 4 homework: 1,2,4,11,20,21, and 25 (extra credit design problem)

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A typical multiplexer lab This is a typical multiplexer lab that students attempted in lab to add an addition two outputs using a block function. This approach was too difficult to solve the control problem so another approach was brainstormed in class. See the next slide.

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Chapter 4 Boolean Logic board work Heuristic proof of DeMorgan Theorems #17— shape shifting properties. Unwritten Booleam Theorem double bar rule and in- class assignment for proving DeMorgan Theorem 16

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More Chapter 4 board work Drawing of Boolean Theorem 14 and results Contrasting ON/OFF control function of basic Boolean Theorems 1, 2, 5, & 6 with OFF highs and OFF lows requiring different devices and inputs.

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Chapter 5—Hardware Descriptive Language Why HDL? HDL Tool Suites HDL-Based Design Flow VHDL Program structure Types, Constants, and Arrays Functions and procedures Libraries Structural Design elements Behavioral Design elements Simulation Test Benches This chapter is covered in Elec 505 course—material is skipped

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Chapter 6—Combinational Logic Design Practices Documentation standards Block diagrams Gate Symbols Signal Names and Active Levels Bubble to bubble logic design Buses Circuit Timing Combinational PLDs Designs: Decoders Encoders Three State Devices Multiplexers Parity circuits Comparators Adders Subtractors ALU Multipliers Chapter homework: TBA (handouts)

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Multiplexer design This is a 3x8 multiplexer lab that was designed in class, completed after the Megafunction Lab, all students got it working.

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Design using TT/SOP/Boolean/reduction/resolution Went heavily into K- maps today to assist the students in the reduction/resolution of the Boolean equations. Used old Chapter 4 power point rather that Boylestad.

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Chapter 7—Sequential Logic Design Principles Bistable elements Metastable behavior Latches and Flip-Flops S-R Latch J-K FF D Latch Edge Triggered D Master-Slave FF State Machine Analysis State Machine Design Designing using State Diagrams Transition Equations Feedback Sequential Circuit Analysis & Design Chapter homework: TBA (handouts)

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Flip Flops-JK In class homework: Complete timing diagram for PGT and NGT Based on Clock pulses the JK output is ½ of clock speed so JK toggle is Divide by 2 or a frequency divider.

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Chapter 8—Sequential Logic Design Practices Timing Diagrams Latches and Flip Flops Switch de-bouncer Bus Holder circuit Registers and Latches Counters Ripple Counter Synchronous counters Shift Registers Ring Counters Johnson Counters Iterative vs. Sequential Circuits Clock skew Gating the clock Asynchronous Inputs Synchronous failure and analysis Chapter homework: TBA (handouts)

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Chapter 9—Memory, CPLDs, and FPGAs Read only memory Read/Write Memory Static RAM Dynamic RAM CPLDs FPGAs Chapter homework: TBA (handouts)

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