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CURRENTLY AND ADVANCED PIXEL DESIGNS FOR HEP Patrick Pangaud Centre de Physique des Particules de Marseille C.P.P.M 163, avenue de Luminy Case 902 13288.

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Presentation on theme: "CURRENTLY AND ADVANCED PIXEL DESIGNS FOR HEP Patrick Pangaud Centre de Physique des Particules de Marseille C.P.P.M 163, avenue de Luminy Case 902 13288."— Presentation transcript:

1 CURRENTLY AND ADVANCED PIXEL DESIGNS FOR HEP Patrick Pangaud Centre de Physique des Particules de Marseille C.P.P.M 163, avenue de Luminy Case Marseille cedex 09 France USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS1

2 HYBRID PIXELS SENSOR FOR HIGH ENERGY PHYSICS IBM 130nm : FEI4 development TSMC 65nm : FEI5 develpment TEZZARON 3D 130nm: FETC4 developments HVCMOS development USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS2

3 Hybrid Pixels Detector for LHC/HL-LHC at CERN USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS3 LHC : Luminosity of cm -2.s -1 HL-LHC expected 10 times more luminosity, more pixels, more ionizing particles, more … !!! Whatever will be discovered in next years at LHC, need much data to understand what has been discovered. Higher luminosity allows extending discovery/studies to higher masses processes of lower cross-section LHC has plans of upgrade by increasing luminosity to collect ultimately ~ 3000 fb -1. This will open new physics possibilities.

4 Inner Tracking ATLAS detector USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS4 Straw tubes Silicon strip Silicon pixel

5 LHC and ATLAS upgrade USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS5 ∫ L dt Year phase-0 phase-1 phase /142018~ TeV → 14 TeV → 2x10 33 cm -2 s -1 → 1x10 34 cm -2 s -1 1x10 34 → ~2x10 34 cm -2 s -1 Now ~10 fb -1 ~50 fb -1 ~300 fb fb -1 → 5x10 34 cm -2 s -1 luminosity leveling Possible upgrade timeline T. Kawamoto, TIPP2011, Chicago, USA

6 ATLAS upgrade USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS6 LHC improves, bulk of luminosity with instantaneous luminosity beyond the nominal luminosity for which the ATLAS detector was designed and built. Technology improves, can build better performing detector now. Detectors age, after the nominal integrated luminosity has been collected, leading to deterioration of performance during the runs at higher luminosity. It will take long time to study and build new detector Installation has to be done during the limited number of long shut downs Installation has to be planned to be prepared to the new running condition T. Kawamoto, TIPP2011, Chicago, USA

7 IBM 130nm FE-I4 DEVELOPMENT USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS7 HYBRID PIXELS SENSOR FOR HIGH ENERGY PHYSICS

8 Hybrid Pixels Sensor for HEP The FE-I4 readout chip 50 μm FE-I3 CMOS technology : 250 nm 400 μm 250 μm FE-I4 CMOS technology : 130 nm Done : ATLAS/LHC (2008/2009) Under Production ATLAS/LHC upgrade project ( ) USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS8 Participating institutes: Bonn Bonn: D. Arutinov, M. Barbero, T. Hemperek, A. Kruth, M. Karagounis. CPPM CPPM: D. Fougeron, M. Menouni. Genova: R. Beccherle, G. Darbo. LBNL LBNL: S. Dube, D. Elledge, M. Garcia-Sciveres, D. Gnani, A. Mekkaoui. Nikhef Nikhef: V. Gromov, R. Kluit, J.D. Schipper FE-I3 FE-I4

9 FE-I4 : Motivation for Redesign of FE USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS9 Need for a new FE? Smaller b-layer radius + potential luminosity increase  higher hit rate.  FE-I3 column-drain architecture saturated.  FE-I4 new digital architecture: local regional memories, stop moving hits around (unless RO).  FE-I4 has smaller pixel (reduced cross-section). New technology:  Higher integration density for digital circuits, rad-hard, availibility μm  130 nm FE-I3  FE-I4 Hit prob. / DC Inefficiency [%] LHC IBL sLHC FE-I3 at r=3.7 cm! The “inefficiency wall” M. Backhaus, FEI4 course, Desy, Germany

10 Future FE-I4-Based Module and Consequences for FE-I4 USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS10 Increased active area: from less than 75 % to ~90 %:  Reduced periphery; bigger IC; cost down for sLHC (main driver is flip-chip costs per chip). No MCC:  More digital functionality in the IC. Power:  Analog design for reduced currents; decrease of digital activity (digital logic sharing for neighbor pixels); new powering concepts. 8 metal layers [2 thick Alu.]  power routing. FE-Chip Sensor Flex ) Big chip (periphery on one side of module). 2) Reduce size of periphery (2.8 mm  2 mm). 3) Thin down FE chips (190 μm  90 μm). 4) Thin down the sensor (250 μm  200 μm)? 5) Less cables (powering scheme)? 5 challenging: power (routing, start-up), clk. distrib., simulation / management, yield 4 M. Backhaus, FEI4 course, Desy, Germany

11 Motivation for Redesign of FE USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS11 Need for a new FE? Accommodate higher hit rate (smaller b-layer radius + luminosity increase)  Architecture based on local memories (no column-drain mechanism). Smaller pixel size: enhanced granularity and reduced cross-section. Reduced periphery & bigger chip: higher active area fraction (<75%  ~90%); cost down for sLHC (main driver is flip-chip, costs per chip). Big chip a challenge: power (routing, start-up), clk. distrib., yield… Simple module: No Module Controller  More digital functions into the FE. Power efficient design & new concepts: Analog design for reduced currents; decrease of digital activity (digital logic sharing for neighbor pixels); new powering concepts. 8 metal layers [2 thick Alu.]  Power routing. New technology: Higher integration density for digital circuits, radiation-hardness (no Enclosed Layout Transistor), availability on timescales of our experiments. M. Backhaus, FEI4 course, Desy, Germany

12 FE-I4 : architecture USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS12 pixel array: 336×80 pixels periphery digital 4-pix analog 1-pix 4-pixel region EODCL DDC Power DOB EOCHL Pads CLKGEN CMD DCD

13 FE-I4 : Digital Region (simplified) USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS13 - Hit Processing - ToT Counter - ToT Memory - Latency Counter - Triggering/Readout  Receiving hit  Start ToT counter  Assign first free memory and latency counter  Generate trailing edge  Store ToT value  Check for trigger when latency counter finished  Indicate ready to read status (release token)  Release memory after read  Read memory  Generate leading edge M. Backhaus, FEI4 course, Desy, Germany

14 TSMC 65NM FE-I5 DEVELOPMENT USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS14 HYBRID PIXELS SENSOR FOR HIGH ENERGY PHYSICS

15 65nm motivations For the HL-LHC (Phase 2) a new pixel detector is planned 2 removable internal layers are planned ( 3.9 cm – 7.5 cm) The event rate is high and the FE-I4 architecture is not adapted The Total Dose is ~ 1GRad A new design is required Reduction of the pixel size for the inner layers R&D : CMOS 65 nm, 3D, Monolithic design CMOS 65 nm is an attractive solution for the development of high-density readout IC. USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS15

16 65nm prototyping  TSMC 65 nm process allows good tolerance to SEU.  However the tolerance of TSMC-ARM digital cells have to be investigated for high dose level : 1000 Mrad Dose effect : Simulations are in progress to check if there are “sensitive” devices inside the Library DFF cell.  New designs are in development :  different structures of configuration memories,  IP blocs : ADC, Voltage reference  First submission of 65nm CMOS IP blocks (plus individual narrow test transistors) is foreseen at CPPM in June or September USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS16

17 TEZZARON 3-D 130nm FE-TC4 DEVELOPMENT USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS17 HYBRID PIXELS SENSOR FOR HIGH ENERGY PHYSICS

18 Outlook 3D project Context : Pixel trackers for high luminosity Tezzaron-Chartered (130nm) 3D run FE-TC4-P1 Bonn/CPPM reticles Delay due to production difficulties Test results : 3D Test results : Analogue part 3D Test results : FE-TC4-AEDS chip 3D Test results : FE-TC4-AEDC chip 2D Chartered chips test results Conclusions and prospects USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS18

19 3-D motivations for ATLAS read-out chip upgrades Improve spatial resolution Deal with an increasing counting rate Decrease pixel size USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS19 50 μm 250 μm FE-I4, 130nm Technology shrinking 3-D benefits : Pixel size reduction Functionalities splitting Technologies mixing Vertical stacking 125 μm 50 μm FE-TC4, 130 nm DIGITAL ANALOG 400 μm 50 μm FE-I3, 250 nm First MPW run for High Energy Physics organized by FNAL with a consortium of 15 institutes. The proposed 3-D process combines : GLOBAL FOUNDRY 130nm technology TEZZARON 3D technology

20 Context : Pixel trackers for high luminosity HL LHC : high luminosity, high pile up, high dose To keep the tracker performance one need to improve pixel granularity : reduce occupancy, improve resolution (and 2 tracks separation), reduce inefficiencies in the readout. Several ways for hybrid pixels detectors move to higher density technologies like 65 nm (shrinking technology ) move to 3D electronics with in-pixel TSVs (vertical stacking) move to CMOS HV (where the sensor can be in the same circuit as the analog amplification) 50 μm 250 μm FE-I4 CMOS 130 nm 125 μm FE-TC4 CMOS 130 nm 2 layers 3D goal : Reduce pixel area without shrinking technology by association of 2 or more layers staked by 3D technologies.  Needs in-pixel communication between the 2 tiers  small TSV  Main 3D advantage : Adequate techno selection for the various functions  Main 3D drawback : Not so easy at the moment USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS20

21 Moore’s law by scaling conventional CMOS involves huge investments. 3D IC processes : An opportunity for another path towards continuing the scaling, involving less investments. Like for conventional CMOS, infrastructures are needed to promote 3D-IC integration, making it available for prototyping at “reasonable” costs. Source IBM 3D-IC Integration The Other Path for Scaling USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS21

22 Why 3-D ? More than Moore… USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS22

23 3-D methods : Through Silicon Vias USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS23

24 3-D methods : Bonding Choices USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS24

25 Understanding the Basic Principles of 3-D Integration Vias Via First – done at foundry, lowest cost Via last – after wafers are made, often done by third party vendors. General movement in industry toward via first approach Bonding options Mechanical bond only, electrical connections later Oxide to oxide bonding Adhesive such as BCB Mechanical and electrical connection formed together CuSn Eutectic CuCu Fusion Direct Bond Interconnect – combination of oxide bonding and metal fusion Thinning Alignment USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS25

26 3-D methods : Areas of Interest to HEP Major Markets being pursued by Industry for 3D integration Pixel arrays for imaging Memory Microprocessors FPGAs … 3-D Pixel arrays with high functionality and smaller form factor for particle tracking 3-D bonding technology to replace bump bonds in hybrid pixel assemblies. USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS26

27  Through silicon Via formation is done either before or after CMOS devices (Front End of Line) processing IBM, NEC, Elpida, OKI, Tohoku, DALSA…. Tezzaron, Ziptronix Chartered, TSMC, RPI, IMEC…….. Form vias before transistors Form transistors before vias 3-D integration : Via First Approach USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS27

28  Via last approach occurs after wafer fabrication and either before or after wafer bonding Zycube, IZM, Infineon, ASET… Samsung, IBM, MIT LL, RTI, RPI…. Notes: Vias take space away from all metal layers. The assembly process is streamlined if you don’t use a carrier wafer. 3-D integration : Via Last Approach USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS28

29 3-D project steps USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS29 Submission / Test March 08 / Summer 08 February 09 / April 09 FEI4_P1 design : IBM 130nm, 8 metals 14x61 "analogue" pixel matrix Pixel size : 50x166µm Rad-hard and SEU tolerance FEC4_P1 circuit : 2D Chartered 130nm, 8 metals Pixel structure : identical to FEI4_P1 (due to schedule no optimization has been done) Objectives : test Chartered technology (functionalities, performances, radiation…) FEC4_P2 circuit : 2D Chartered, 8 metals Based on FEC4_P1 circuit, plus : Optimization of transistors New latches for irradiation tests New PadRing strategy and ground/substrate separation FEC4_P3 : 2D Chartered, 8 metals but only 5 are used) Smaller pixel size : 50µm x 125µm Design of new sub-circuits and functionalities : Analogue multiplexor and Triple redundancy memory Calibration (pulse generator) PLL LVDS and ESD I/O Pads Nov 09 / Jan 10 Nov 10 / Nov 11

30 3-D project steps First 3-D design (MPW organized by FNAL) FE-TC4_P1 project Global Foundries 130 nm (5 metal levels) + Tezzaron One Tier for the analogue pixel part : 14x61 pixel matrix Pixel size : 50x166µm One Tier for the digital part Two versions have been designed : one dedicated for test, (FE-TC4-DS) one “FE-I4-like”.,(FE-TC4-DC) USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS30 July 09 / now Submission / Test

31 Tezzaron-Chartered 3-D technology USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS31 Main characteristics : 2 wafers (tier 1 and tier 2) are stacked face to face with Cu- Cu thermo-compression bonding Via Middle technology : Super-Contacts (Through Silicon contacts) are formed before the BEOL of Chartered technology. Wafer is thinned to access Super-Contacts Chartered 130nm technology limited to 5 metal levels Back-side metal for bonding (after thinning) One tier Bond interface layout Wafer to wafer bonding

32 Tezzaron-Chartered (130nm) 3D run 3D consortium created in 2008 (with MAPS and Hybrid pixels communities) and 3D MPW run in 2009 Main technology features  130 nm  Large reticle (≈26 x 30 mm)  6 metal levels (M6 is the bond interface)  Wafer to wafer, face to face bonding  TSV Vias 1.2 µm diameter with 3.8 µm recommended pitch (Via Middle Techno)  Bond interface : copper (regular pattern)  Upper tier thinned down to 10 µm M5 M4 M3 M2 M1 M6 Super Contact M1 M2 M3 M4 M5 M6 Super Contact Bond Interface Tier 2 Tier 1 (thinned wafer) Back Side Metal sensor USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS32

33 Fermilab 3-D Multi-Project Run  Fermilab has planned a dedicated 3-D multi project run using Tezzaron for HEP during 2009  There are 2 layers of electronics fabricated in the Chartered 0.13 um process, using only one set of masks. (Useful reticule size 15.5 x 26 mm)  The wafers are bonded face to face. ATLAS/SLHC Sub-part USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS33

34 FE-TC4-P1 Bonn/CPPM reticles The reticles contains : the analog tier : FE-TC4-AE : Pixel matrix of 14 x 61 pixels, pixel size 50x166 µm. Analog tier is very close to FE-C4-P1 (GF version of FE-I4-P1) 2 flavors of digital tier : FE-TC4-DS : digital tier with simple read-out (one-bit latch/ pixel), dedicated for studying coupling between tiers FE-TC4-DC : digital tier with complex readout “a la FEI4” (Bonn) SEU3D : SEUless memory blocks General Test structures : TSV + BI Daisy chain, transistors, etc… USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS34

35 Delay due to production difficulties Analog tier completely removed during thinning + misalignment of bond interface between two tiers  First 3D assemblies AE- DC and AE-DS arrived in September 2011 with damages.  First tests in 2011 : Analog tier, DC tier, DS tier tested separately in standard thicknesses (February 2011)  First 3D working chips in 2012 ! First 3D wafers with defects visible to the naked eye USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS35

36 FE-TC4-AE analogue tier USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS36 Based on FE-C4_P1 chip + all adds for 3-D connection Input signal from sensor via the Super-Contacts Bonding pad in Back-side metal 2 possible ways for discriminator output read-out: With the simple read-out part existing yet into the pixel With the tier 2 (via the Bond Interface) Additional switch for read-out

37 3D Test results : FETC4_AE results The analogue Tier is thinned. The output of the comparator can be read directly in the analog tier or in the digital tier via the bond interface (in the same time!) Noise < 100 e- rms  The 10 µm thick analog pixel behaves as un-thinned one. USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS37

38 FE-TC4-DS digital tier for test USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS38 Analogue tier and digital tier are face to face (sensitive part facing digital part). FE-TC4-DS : dedicated for parasitic coupling studies between the 2 tiers. 3 functions : Read the discriminator output Generate noise (digital commutations) in front of 11 specific areas of the analogue pixel (preamplifier, feed-back, amplifier2, DAC…) Test different shielding configurations. Analogue pixel layout : 11 specific areas ANALOGUE DIGITAL

39 3D Test results : FE-TC4-AEDS chip Analogue and Digital Simple tiers communicate ! USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS39

40 3D Test results : FE-TC4-AEDS chip Shielding studies with Digital Simple The DS chip contains : a simple readout system (one- bit latch/ pixel), a counter, 11 DRUM cells (noise generators to study the coupling between tiers) which can be activated individually.  Each DRUM cell layout is facing one specific area (sub-part) of the analog pixel.  To test the intra-pixel sensitivity. A simple way to generate noise and test the influence on the analogue Tier. USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS40

41 3D Test results : FE-TC4-AEDS chip Shielding studies with Digital Simple Moreover, to determine the best shielding strategy, different metal shielding have been implemented on the DS chip : Sh i e l d M e t al 3 a n d M etal 5 Sh i e l d M e t al 5 No Sh i e l d Sh i e l d Me t a l 3 No S hi e l d Shielding configuration depending on column numbers :  Col 0 and 1 => shield in Metal 3 and Metal 5  Col 2, 3, 4, 5 => shield in Metal 5  Col 6, 7, 8 => no shield  Col 9 and 10 => shield in Metal 3  Col 11, 12, 13 => no shielded USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS41

42 3D Test results : FE-TC4-AEDS chip Shielding studies with Digital Simple First try  Comparison No Drums / All Drums S curves measurements noise = 116 e- 150 e- 250 e- 350 e- 800 e-  A shielding is necessary.  Shielding with only M3 is not enough efficient.  Metal 5 appears to be the best solution. USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS42

43 3D Test results : FE-TC4-AEDS chip Shielding studies with Digital Simple  Studying the intra-pixel sensitivity  Each drum is separately activated. The noise is measured on column 7 (without any shield) (noise of 116e- with all drum OFF).  The most sensitive parts are those directly connected to the input (bump area, injection capacitor) : Not a big surprise but it confirms that the others parts are not sensitive to the digital tier. 119 e- 400 e- 200 e- 119 e- 500 e- 350 e- 120 e- 121 e- 124 e- 119 e- 120 e- USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS43

44 3D Test results : FE-TC4-AEDC chip Digital Complex chip offers a complex read-out "A la FE-I4” (with 4 pixel regions). The FE-TC4-AEDC is fully tested by Bonn University : Threshold~2400e- Noise~94e- The tuned threshold can reach a dispersion of 50e-.  The AE tier and DC tier communicates wells.  The analogue performances are as expected.  The readout with TOT information has been tested and works as expected. USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS44

45 3D Test results : FE-TC4-AEDC chip Study of crosstalk between pixel Test procedure: Inject charge to two pixels and read out only the pixel in between. Cover the matrix with a 16 Step mask. Configuration : Tuned threshold around ~ 2800 electrons (for the pixel in the middle) The injection is increased until reach the crosstalk threshold for which the middle pixel is affected. Crosstalk threshold = Normal Threshold / Threshold Measured with crosstalk mask 16 Step Mask First step Inject Read USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS45

46 3D Test results : FE-TC4-AEDC chip Study of crosstalk between pixel Threshold ~31680 e- Threshold ~31810 e- Crosstalk threshold ~ 4,42% Crosstalk threshold ~ 4,40% Read analog tier Read digital tier The crosstalk threshold is the same if the readout is done via the analog shift register or the digital shift register : The main crosstalk path is on the analog tier only. No addition of crosstalk through the digital tier is observed. USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS46

47 3D Project : test structures From the first 3D prototype made for the ATLAS Project, some test were done to measure TSV and Bond-Interface performance. The TSV (Through Silicon Via) consists of a vertical conductor, often referred to as “nail” or “plug”, entirely crossing the Si substrate of the stacked dies. Measure the TSV daisy chain(51520 tsv), to understand its electrical properties. USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS47

48 FE-TC4-P1 TSV and BI test We measured 19 chips, which show good tsv daisy chain interconnection. Yielding ~84%. Single tsv resistance is. Agree with reference value <600mohm(Tezzaron report) Single tsv capacitance(metal-insulator-semiconductor) in inversion region is around 5.5fF. The calculated value is 3.6fF. In addition, we cannot measure accumulation region capacitance because ESD diodes limit bias voltage. The BI test results reveal some problems. Only 1 chip shows good interconnection. Perhaps the alignment issues and chip surface irregularities lead to these problems. USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS48

49 Single 2D FE-C4_Px test results All prototypes showed excellent results Un-tuned FEC4_P1 threshold dispersion around 200 e- FEC4_P1 Noise lower than 100 e- rms FEC4_P1 Power consumption 27µA/pixel USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS49 Irradiation performed at CERN/PS facility (24 GeV protons)

50 FEC4-P3 test results under radiation Third 2D chip in Chartered 130nm ( submitted in 2011) : Smaller pixel size (50µm x 166µm => 50µm x 125µm) Design of new sub-parts : analogue buffer, analogue multiplexor …. Radiation Hardness improvement (optimized latches, substrate separation, guard-ring…) Tests under radiation at CERN/PS : The test was made up to 650 MRads. The chip resists well : up to 300 MRads for the Analog Part and up to the end of the campaign for the Digital Part. The chip is not broken after irradiation, and works. The Analog Part shows a good annealing recovering after 6 months (after irradiation: 78% of dead pixels, after 6 months of annealing: 18% of dead pixels). The new small analog pixel is now completely ready for a next 3D integration. USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS50

51 FEC4-P3 : Analog behavior before protons beam USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS51 At 0 Mrad Sigma Threshold = 674 e- Mean Noise = 339 e- The nominal noise is 100e-, but we ever detected some excess noise by using the USBPix card (200e-)

52 FEC4-P3 : Analog behavior under protons beam USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS52 At 594Mrads Sigma Threshold = ????? Mean Noise = ????? 3/05/ /05/ /05/ /05/2012 Beam Fluence

53 FEC4-P3 : Analog behavior after 203 days annealing USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS53

54 The FE-TC4 ATLAS full-scale chip USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS54 FE-TC4, run 3-D Very large matrix size : 336 x 160 pixels Chip size of 18.8 x 20.1 mm mm End Of Column width. Small pixel size : 125µm x 50µm Bump bond pads compatible with 250 µm sensor pitch (FE-I4 project) The FE-TC4 re-uses main blocks of FE- I4 to be compatible for sensors, bump bonding, module/stave integration, testing tools, software, mechanics FE-I3 FE- TC 4 160

55 Conclusions and prospects The Global Foundry 130nm is a good candidat with good electrical performance under protons radiation Despite the (very) poor yield the Tezzaron-Chartered technology is finally working and gives very good results. Substantial efforts have to be made by vendors to improve yield and delivery schedule. Next step : Hybridization of a sensor in such a 3D wafer If the sensor hybridization on a 10µm thinned tier works, this 3D process will be a success. In parallel, we work with HV-CMOS technology which can allow to perform 3D stacking without the sensor hybridization step (reduce of cost, time and complexity). We are working firstly with the Chartered HV technology (BCDlite) in view of a Chartered-Tezzaron 3D processing (2D MPW run in May 2012). But if this technology would appear to be not suitable, we could try to use Tezzaron process with another HV technology (as allowed in 3D process). Sensor layout : Anna Macchiolo, Max- Planck-Institut für Physik, Munich  USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS55

56 HVCMOS DEVELOPMENT USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS56 HYBRID PIXELS SENSOR FOR HIGH ENERGY PHYSICS

57 SMART Diode in CMOS technology 57 The CMOS signal processing electronics are placed inside the deep-n-well. PMOS are placed directly inside n-well, NMOS transistors are situated in their p-wells that are embedded in the n-well as well. Ivan Peric, FEE2011, Bergamo, Italy USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS

58 USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS58

59 USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS59

60 A new 3D approach for HEP community M6 TSV Bond Interface Tier 2 Smart Sensor Tier 1 (thinned wafer) Back Side Metal M5 M4 M3 M2 M1 M2 M3 M4 M5 M4 M3 M2 M1 M2 M3 M4 M5 particle Global Foundries BCDLite technology 0,13µm Electrical field TSV technologies (Via last or middle or first) GlobalFoundries 0,13µm BCDLite technology The BCDLite include the Low power option plus the High Voltage option. Bond Interface : regular Redistribution Layer made with last thick Cu Top Metal (1µm) 6 metal levels Large reticle (≈26 x 30 mm) Upper tier thinned down The HV-CMOS technology allows to perform 3D stacking without the sensor hybridization step (reduce of cost, time and complexity). Because the Tezzaron-Chartered technology is a good rad- hard candidate, we will use the enhanced GlobalFoudry BCDLite technology to design a new chip in spring 2013 Can we mix the smart diode and the 3D Integrated technology? USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS60

61 IBM 130nm: Possible well-substrate configuration 61 Nwell Pwell Deep Nwell P- (1-2 Ohm-cm) NwellPwell T3 “Burried n” P- (1-2 Ohm-cm) P- Nwell Pwell P- (1-2 Ohm-cm) Conventional T3: True isolation. NMOS and PMOS on top of sensor. Substrate can be biased. Proposed prototype to study such a sensor! Deep Nwell: more flexible - sub can be biased VSUB 0 to -10V USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS

62 Conclusion Time to R&D, between LHC phases Several approach for the same goal : Compactness information on less mass material. Using the 3-D electronic integration approach Using very deep submicronic technology (65nm technology…) Using the HVCMOS …. Or all in one We need to create, design and test to qualify these new approaches New technologies (deeper submicronic, 3D ways, Smart pixels…) New industrial, academic partners, new alliances Novel architecture (analog detection and digital post-processing) Radiation hardness ( protons beam, Gamma ray, etc…) Robustness by test We would like to thank the fruitful collaboration with Wei Wei, Lei Zhao, Luo Jianping, Wang Zheng Na Wang, Jiang Xiaoshan, Fu Wei, Jian Lu USTC, April 11, 2013Patrick Pangaud - CPPM-IN2P3-CNRS62


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