Download presentation

Presentation is loading. Please wait.

Published byRaphael Burridge Modified over 2 years ago

1
CSE 205: D IGITAL L OGIC D ESIGN Prepared By, Dr. Tanzima Hashem, Assistant Professor, CSE, BUET Updated By, Fatema Tuz Zohora, Lecturer, CSE, BUET

2
S EQUENTIAL C IRCUITS Consist of a combinational circuit to which storage elements are connected to form a feedback path State: the state of the memory devices now, also called current state Next states and outputs are functions of inputs and present states of storage elements

3
A LARM CONTROL SYSTEM Suppose we wish to construct an alarm circuit such that the output remains active (on) even after the sensor output that triggered the alarm goes off The circuit requires a memory element to remember that the alarm has to be active until a reset signal arrives

4
T WO T YPES OF S EQUENTIAL C IRCUITS Asynchronous sequential circuit Depends upon the input signals at any instant of time and their change order May have better performance but hard to design Synchronous sequential circuit Defined from the knowledge of its signals at discrete instants of time Much easier to design (preferred design style) Synchronized by a periodic train of clock pulses

5
S YNCHRONOUS S EQUENTIAL C IRCUITS

6
M EMORY ELEMENTS Latch - a level-sensitive memory element SR latches D latches Flip-Flop - an edge-triggered memory element Master-slave flip-flop Edge-triggered flip-flop RAM and ROM a mass memory element C CLKPositive Edge CLKNegative Edge

7
L ATCHES A latch is binary storage element Can store a 0 or 1 The most basic memory Easy to build Built with gates (NORs, NANDs, NOT)

8
L ATCHES S R Q 0 QQ’ 0 0 0 0 1 0 0 01 Q = Q 0 Initial Value SR Latch

9
L ATCHES S R Q 0 Q Q’ 0 0 001 0 0 1 1 0 0 0 10Q = Q 0 SR Latch

10
L ATCHES S R Q 0 Q Q’ 0 0 001 0 0 110 0 1 00 0 1 1 0 1 Q = 0 Q = Q 0 SR Latch

11
L ATCHES S R Q 0 Q Q’ 0 0 001 0 0 110 0 1 001 0 1 1 1 0 1 0 01 Q = 0 Q = Q 0 Q = 0 SR Latch

12
L ATCHES S R Q 0 Q Q’ 0 0 001 0 0 110 0 1 001 0 1 101 1 0 0 0 1 0 1 10 Q = 0 Q = Q 0 Q = 1 SR Latch

13
L ATCHES S R Q 0 Q Q’ 0 0 001 0 0 110 0 1 001 0 1 101 1 0 010 1 0 1 1 0 0 1 10 Q = 0 Q = Q 0 Q = 1 SR Latch

14
L ATCHES S R Q 0 Q Q’ 0 0 001 0 0 110 0 1 001 0 1 101 1 0 010 1 0 110 1 1 0 0 1 1 1 00 Q = 0 Q = Q 0 Q = 1 Q = Q’ 0 SR Latch

15
L ATCHES S R Q 0 Q Q’ 0 0 001 0 0 110 0 1 001 0 1 101 1 0 010 1 0 110 1 1 000 1 1 1 1 0 1 1 00 Q = 0 Q = Q 0 Q = 1 Q = Q’ 0 SR Latch

16
SR L ATCH S RQ 0 Q0Q0 0 10 1 01 1 Q=Q’=0 No change Reset Set Invalid S R Q 0 Q=Q’=1 0 11 1 00 1 Q0Q0 Invalid Set Reset No change

17
SR L ATCH S RQ 0 Q0Q0 0 10 1 01 1 Q=Q’=0 No change Reset Set Invalid S’ R’Q 0 Q=Q’=1 0 11 1 00 1 Q0Q0 Invalid Set Reset No change

18
C ONTROLLED L ATCHES C S RQ 0 x x Q0Q0 1 0 0 Q0Q0 1 0 10 1 1 01 1 1 1Q=Q’Q=Q’ No change Reset Set Invalid SR Latch with Control Input

19
C ONTROLLED L ATCHES C DQ 0 x Q0Q0 1 00 1 1 No change Reset Set C Timing Diagram D Q t Output may change D Latch (D = Data)

20
C ONTROLLED L ATCHES C DQ 0 x Q0Q0 1 00 1 1 No change Reset Set C Timing Diagram D Q Output may change D Latch (D = Data)

21
C ONTROLLED L ATCHES JK Latch

22
C ONTROLLED L ATCHES T - Latch

23
G RAPHIC SYMBOLS FOR LATCHES

24
L EVEL VERSUS EDGE SENSITIVITY Since the output of the D latch is controlled by the level (0 or 1) of the clock input, thelatch is said to be level sensitive All of the latches we have seen have been level sensitive It is possible to design a storage element for which the output only changes a the point in time when the clock changes from one value to another Such circuits are said to be edge triggered

25
Controlled latches are level-triggered Flip-Flops are edge-triggered F LIP -F LOPS C CLKPositive Edge CLKNegative Edge

26
F LIP -F LOPS DQ Q DQ Q Positive Edge Negative Edge Edge-Triggered D Flip-Flop (positive edge triggered) Three SR Latch

27
Edge-Triggered D Flip-Flop F LIP -F LOPS 0 1 1 No change in output 0 S R Q 0 Q=Q’=1 0 11 1 00 1 Q0Q0 Invalid Set Reset No change

28
Edge-Triggered D Flip-Flop F LIP -F LOPS 0 1 1 1 S R Q 0 Q=Q’=1 0 11 1 00 1 Q0Q0 Invalid Set Reset No change No change in output

29
Edge-Triggered D Flip-Flop F LIP -F LOPS 1 1 1 0 1 1 1 0 0 S R Q 0 Q=Q’=1 0 11 1 00 1 Q0Q0 Invalid Set Reset No change Reset State If D = 0 when CLK turns from 0 to 1, R → 0, Q = 0 1

30
Edge-Triggered D Flip-Flop F LIP -F LOPS 1 1 0 1 1 1 0 0 S R Q 0 Q=Q’=1 0 11 1 00 1 Q0Q0 Invalid Set Reset No change Reset State After reaching Reset State, while CLK = 1, what happens if D changes to 1?

31
Edge-Triggered D Flip-Flop F LIP -F LOPS 1 1 1 1 0 0 0 1 S R Q 0 Q=Q’=1 0 11 1 00 1 Q0Q0 Invalid Set Reset No change Set State If D = 1 when CLK turns from 0 to 1, R → 0, Q = 0 0 0

32
Edge-Triggered D Flip-Flop F LIP -F LOPS 1 0 1 1 0 0 0 1 S R Q 0 Q=Q’=1 0 11 1 00 1 Q0Q0 Invalid Set Reset No change Set State After reaching Set State, while CLK = 1, what happens if D changes to 0?

33
F LIP -F LOPS : E DGE -T RIGGERED D F LIP -F LOP

34
F LIP -F LOPS If D = 0 when CLK turns from 0 to 1, R → 0, Q = 0: ‘reset state’ If D changes while CLK is high →flip-flop will not respond to the change. When CLK turns from 1 to 0, Q = 0:, R → 1, flip- flop will be in the same state (no change in output). If D = 1 when CLK from 0 to 1, S →0, Q = 1: ‘set state’

35
JK Flip-Flop F LIP -F LOPS D = JQ’ + K’Q JQ QK

36
JK Flip-Flop When J = 1 and K = 0, D = 1 → next clock edge sets output to 1. F LIP -F LOPS D = JQ’ + K’Q

37
JK Flip-Flop When J = 0 and K = 1, D = 0 → next clock edge resets output to 0. F LIP -F LOPS D = JQ’ + K’Q

38
JK Flip-Flop When J = 1 and K = 1, D = Q’ → next clock edge complements output. F LIP -F LOPS D = JQ’ + K’Q

39
T Flip-Flop F LIP -F LOPS D = TQ’ + T’Q = T Q JQ QK T DQ Q T D = JQ’ + K’Q TQ Q

40
M ASTER -S LAVE F LIP -F LOPS D Latch (Master) DCDC Q D Latch (Slave) DCDC QQD CLK D Q Master Q Slave Looks like it is negative edge-triggered MasterSlave Master-Slave D Flip-Flop (negative edge triggered)

41
M ASTER -S LAVE F LIP -F LOPS The circuit samples the D input and changes its output at the negative edge of the clock, CLK. When the clock is 0, the output of the inverter is 1. The slave latch is enabled and its output Q is equal to the master output Y. The master latch is disabled ( CLK = 0). When the CLK changes to high, D input is transferred to the master latch. The slave remains disabled as long as CLK is low. Any change in the input changes Y,but not Q. The output of the flip-flop can change when CLK makes a transition 1 → 0

42
Master Slave SR Flip-Flop (negative edge triggered) M ASTER -S LAVE F LIP -F LOPS

43
Master Slave JK Flip-Flop (negative edge triggered) M ASTER -S LAVE F LIP -F LOPS

44
F LIP -F LOP C HARACTERISTIC T ABLES DQ Q DQ(t+1) 00 11 Reset Set JKQ(t+1) 00Q(t)Q(t) 010 101 11Q’(t) No change Reset Set Toggle JQ QK TQ Q TQ(t+1) 0Q(t)Q(t) 1Q’(t) No change Toggle

45
F LIP -F LOP C HARACTERISTIC E QUATIONS DQ Q DQ(t+1) 00 11 Q(t+1) = D JKQ(t+1) 00Q(t)Q(t) 010 101 11Q’(t) Q(t+1) = JQ’ + K’Q JQ QK TQ Q TQ(t+1) 0Q(t)Q(t) 1Q’(t) Q(t+1) = T Q

46
Asynchronous Reset F LIP -F LOPS WITH D IRECT I NPUTS DQ Q R Reset R’DCLKQ(t+1) 0xx0 10 ↑ 0 11 ↑ 1

47
Asynchronous Reset Connect the Reset Input such that Reset=0 will immediately make Q=0 (Reset state) F LIP -F LOPS WITH D IRECT I NPUTS 0 1 1 0 1 1 0 0 0

48
Asynchronous Preset and Clear F LIP -F LOPS WITH D IRECT I NPUTS PR’CLR’DCLKQ(t+1) 10xx0 01x x 1 110 ↑ 0 111 ↑ 1 DQ Q CLR Reset PR Preset

49
A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS : T HE S TATE State = Values of all Flip-Flops Example A B = 0 0

50
A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS : T ERMINOLOGY State Equation : A state equation (transition equation) specifies the next state as a function of the present state and inputs. State Table: A state table (transition table) consists of: present state, input, next state and output. State Diagram: The information in a state table can be represented graphically in a state diagram. The state is represented by a circle and the transitions between states are indicated by directed lines connecting the circles.

51
Input Equation: D A = A(t)x(t) + B(t)x(t) D B = A’(t)x(t) Output Equation: y(t) = [A(t)+ B(t)] x’(t) = (A + B) x’ State Equation: A(t+1) = D A = A(t) x(t)+B(t) x(t) = A x + B x B(t+1) = D B = A’(t) x(t) = A’ x A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS : S TATE /T RANSITION E QUATIONS

52
A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS : S TATE /T RANSITION T ABLE A(t+1) = A x + B x B(t+1) = A’ x y(t) = (A + B) x’ Present State Input Next State Output ABxABy 000 001 010 011 100 101 110 111 t+1 t t 0 0 0 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 1 1 0 0

53
A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS : S TATE /T RANSITION T ABLE A(t+1) = A x + B x B(t+1) = A’ x y(t) = (A + B) x’ Present State Next StateOutput x = 0x = 1x = 0x = 1 ABABAB yy 00000100 01001110 10001010 11001010 t+1 t t

54
54 0 1 0 0 11 0/00/0 0/10/1 1/01/0 1/01/0 1/01/0 1/01/00/10/1 0/10/1 AB input/output Present State Next StateOutput x = 0x = 1x = 0x = 1 ABABAB yy 00000100 01001110 10001010 11001010 A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS : S TATE D IAGRAM

55
Example : A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS : D F LIP -F LOPS DQ Q x CLK y A Present State Input Next State AxyA 000 001 010 011 100 101 110 111 0 1 1 0 1 0 0 1 01 00,11 01,10 State Equation: A(t+1) = D A = A x y Input Equation: D A = A x y No Output column / Output Equation (Output = Next State)

56
Example : A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS : JK F LIP -F LOPS J A = BK A = B x’ J B = x’K B = A x A(t+1) = J A Q’ A + K’ A Q A = A’B + AB’ + Ax B(t+1) = J B Q’ B + K’ B Q B = B’x’ + ABx + A’Bx’ Present State I/P Next State Flip-Flop Inputs ABxABJAJA KAKA JBJB KBKB 000 001 010 011 100 101 110 111 0 0 1 0 0 0 0 1 1 1 1 0 1 0 0 1 0 0 1 1 0 0 1 1 1 0 0 0 0 1 0 1 1 0 1 1 0 0 1

57
A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS : JK F LIP -F LOPS Present State I/P Next State Flip-Flop Inputs ABxABJAJA KAKA JBJB KBKB 000 001 010 011 100 101 110 111 0 0 1 0 0 0 0 1 1 1 1 0 1 0 0 1 0 0 1 1 0 0 1 1 1 0 0 0 0 1 0 1 1 0 1 1 0 0 1 0 1 0 11 0 101 0 1 0 0 1 Example :

58
A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS : T F LIP -F LOPS T A = B xT B = x y = A B A(t+1) = T A Q’ A + T’ A Q A = AB’ + Ax’ + A’Bx B(t+1) = T B Q’ B + T’ B Q B = x B Present State I/P Next State F.F Inputs O/P ABxABTATA TBTB y 000 001 010 011 100 101 110 111 0 0 1 0 1 0 0 1 0 1 0 0 1 1 0 1 0 0000001100000011

59
A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS : T F LIP -F LOPS Present State I/P Next State F.F Inputs O/P ABxABTATA TBTB y 000 001 010 011 100 101 110 111 0 0 1 0 1 0 0 1 0 1 0 0 1 1 0 1 0 0000001100000011 0 1 1 1 0 0/00/0 1/01/0 0/00/0 1/01/0 1/01/0 1/11/1 0/00/0 0/10/1 Example :

60
P RACTICE A sequential circuit with two D flip-flops A and B. two inputs x and y, and one output z is specified by the following next-state and output equations A(t + 1 ) = x ’ y + x B B(t + 1 ) = x ’ A + x B z = B Draw the logic diagram of the circuit. List the stale table for the sequential circuit. Draw the corresponding state diagram.

61
P RACTICE

64
M EALY AND M OORE M ODELS The Mealy model: the outputs are functions of both the present state and inputs The outputs may change if the inputs change during the clock pulse period. The outputs may have momentary false values unless the inputs are synchronized with the clocks. The Moore model: the outputs are functions of the present state only The outputs are synchronous with the clocks.

65
M EALY AND M OORE M ODELS Block diagram of Mealy and Moore state machine

66
M EALY AND M OORE M ODELS Present State I/P Next State O/P ABxABy 000000 001010 010001 011110 100001 101100 110001 111100 Mealy state outputinput For the same state, the output changes with the input Present State I/P Next State O/P ABxABy 000000 001010 010010 011100 100100 101110 110111 111001 Moore state outputinput For the same state, the output does not change with the input

67
M OORE S TATE D IAGRAM State / Output 0 0 / 00 1 / 0 1 1 / 11 0 / 0 0 1 1 1 00 0 1

68
S TATE REDUCTION Sequential circuit analysis Circuit diagram state table (or state diagram) Sequential circuit design State diagram (state table) circuit diagram Redundant state may exist in a state diagram (or table) By eliminating them reduce the # of logic gates and flip-flops

69
Eastern Mediterranean University S TATE R EDUCTION Only the input-output sequences are important. Initial state is a In state a, for input=0, output is 1, and next state is a In state a, for input=1, output is 0, and next state is b..and so on. State diagram State:aabcdeffgfga Input:01010110100 Output : 00000110100 Initial State is a

70
Eastern Mediterranean University S TATE R EDUCTION Two circuits are equivalent Have identical outputs for all input sequences; The number of states is not important. State diagram State:aabcdeffgfga Input:01010110100 Output : 00000110100 Initial State is a

71
S TATE R EDUCTION Equivalent states Two states are said to be equivalent For each member of the set of inputs, they give exactly the same output and send the circuit to the same state or to an equivalent state. One of them can be removed.

72
S TATE R EDUCTION 1. e = g (remove g ); 2. Replace all g by e

73
S TATE R EDUCTION Reducing the state table d = f (remove f );

74
S TATE R EDUCTION The reduced finite state machine State:aabcdeddedea Input:01010110100 Output: 00000110100

75
S TATE R EDUCTION : I MPLICATION T ABLE The state-reduction procedure for completely specified state tables is based on the algorithm that two states in a state table can be combined into one if they can be shown to be equivalent. There are occasions when a pair of states do not have the same next states, but, nonetheless, go to equivalent next states The checking of each pair of states for possible equivalence in a table with a large number of states can be done systematically by means of an implication table.

76
( a, b ) imply ( c, d ) and ( c, d ) imply ( a, b ). Both pairs of states are equivalent; i.e., a and b are equivalent as well as c and d. 76 S TATE R EDUCTION : I MPLICATION T ABLE

78
b c d e f g abcdef On the left side along the vertical are listed all the states defined in the state table except the first across the bottom horizontally are listed all the states expect the last

79
b c d e f g abcdef d-e we place a cross in any square corresponding to a pair of states whose outputs are not equal for every input. Otherwise, we enter the pairs of states that are implied by the pair of states representing the squares.0 we place a tick in any square corresponding to a pair of states whose outputs and next states are equal for every input.

80
d-c a-b c-e a-b b c d e f g abcdef d-e

81
d-c a-b c-e a-b b c d e f g abcdef d-e

82
d-c a-b c-e a-b b c d e f g abcdef d-e

83
d-c a-b c-e a-b b c d e f g abcdef d-e

84
d-c a-b c-e a-b b c d e f g abcdef d-e

85
d-c a-b c-e a-b b c d e f g abcdef d-e The next step is to make successive passes through the table to determine whether any additional squares should be marked with a cross or tick A square in the table is crossed out if it contains at least one implied pair that is not equivalent

86
S TATE R EDUCTION : I MPLICATION T ABLE Finally, all the squares that have no crosses are recorded with check marks. The equivalent states are: ( a, b ), ( d, e ), ( d, g ), ( e, g ). We now combine pairs of states into larger groups of equivalent states. The last three pairs can be combined into a set of three equivalent states ( d, e, g ) because each one of the states in the group is equivalent to the other two.

87
d-e d-c a-b c-e a-b b c d e f g abcdef d-e

88
S TATE R EDUCTION : I MPLICATION T ABLE The final partition of these states consists of the equivalent states found from the implication table, together with all the remaining states in the state table that are not equivalent to any other state: ( a, b ) ( c ) ( d, e, g ) ( f )

89
S TATE A SSIGNMENT Assign coded binary values to the states for physical implementation For a circuit with m states, the codes must contain n bits where 2 n >= m Unused states are treated as don’t care conditions during the design Don’t cares can help to obtain a simpler circuit There are many possible state assignments Have large impacts on the final circuit size

90
P OPULAR S TATE A SSIGNMENT

91
S TATE A SSIGNMENT Any binary number assignment is satisfactory as long as each state is assigned a unique number Use binary assignment 1

92
D ESIGN P ROCEDURE Derive a state diagram for the circuit from specifications Reduce the number of states if necessary Assign binary values to the states Obtain the binary-coded state table Choose the type of flip-flop to be used Derive the simplified flip-flop input equations and output equations Draw the logic diagram

93
D ESIGN P ROCEDURE Derive a state diagram for the circuit from specifications Reduce the number of states if necessary Assign binary values to the states Obtain the binary-coded state table Choose the type of flip-flop to be used Derive the simplified flip-flop input equations and output equations Draw the logic diagram

94
D ESIGN OF C LOCKED S EQUENTIAL C IRCUITS S0 / 0S0 / 0S 1 / 0 S 3 / 1S 2 / 0 0 1 1 0 0 1 0 1 StateA B S0S0 0 S1S1 0 1 S2S2 1 0 S3S3 1 Example : Detect 3 or more consecutive 1’s

95
D ESIGN OF C LOCKED S EQUENTIAL C IRCUITS Present State Input Next State Output ABxABy 000 001 010 011 100 101 110 111 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 1 S0 / 0S0 / 0S 1 / 0 S 3 / 1S 2 / 0 0 1 1 0 0 1 0 1 Example : Detect 3 or more consecutive 1’s

96
Example : Detect 3 or more consecutive 1’s D ESIGN OF C LOCKED S EQUENTIAL C IRCUITS Present State Input Next State Output ABxABy 000 001 010 011 100 101 110 111 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 1 A(t+1) = D A (A, B, x) = ∑ (3, 5, 7) B(t+1) = D B (A, B, x) = ∑ (1, 5, 7) y (A, B, x) = ∑ (6, 7) D Synthesis using D Flip-Flops

97
D ESIGN OF C LOCKED S EQUENTIAL C IRCUITS WITH D F.F. D A (A, B, x) = ∑ (3, 5, 7) = A x + B x D B (A, B, x) = ∑ (1, 5, 7) = A x + B’ x y (A, B, x) = ∑ (6, 7) = A B D Synthesis using D Flip-Flops B 0010 A0110 x B 0100 A0110 x B 0000 A0011 x Example : Detect 3 or more consecutive 1’s

98
Example : Detect 3 or more consecutive 1’s D ESIGN OF C LOCKED S EQUENTIAL C IRCUITS WITH D F.F. D A = A(t+1) = A x + B x D B = B(t+1) = A x + B’ x y = A B D Synthesis using D Flip-Flops

99
99 F LIP -F LOP E XCITATION T ABLES Present State Next State F.F. Input Q(t)Q(t)Q(t+1)JK 00 01 10 11 0 x 1 x x 1 x 0

100
100 F LIP -F LOP E XCITATION T ABLES Present State Next State F.F. Input Q(t)Q(t)Q(t+1)D 00 01 10 11 Present State Next State F.F. Input Q(t)Q(t)Q(t+1)JK 00 01 10 11 0 0 (No change) 0 1 (Reset) 0 x 1 x x 1 x 0 0 1 0 1 1 0 (Set) 1 1 (Toggle) 0 1 (Reset) 1 1 (Toggle) 0 0 (No change) 1 0 (Set) Q(t)Q(t)Q(t+1)T 00 01 10 11 0 1 1 0

101
D ESIGN OF C LOCKED S EQUENTIAL C IRCUITS WITH JK F.F. Present State Input Next State Flip-Flop Inputs ABxAB JAJA KAKA JBJB KBKB 00000 00101 01000 01110 10000 10111 11000 11111 0 x 1 x x 1 x 0 x 1 x 0 J A (A, B, x) = ∑ (3) d JA (A, B, x) = ∑ (4,5,6,7) K A (A, B, x) = ∑ (4, 6) d KA (A, B, x) = ∑ (0,1,2,3) J B (A, B, x) = ∑ (1, 5) d JB (A, B, x) = ∑ (2,3,6,7) K B (A, B, x) = ∑ (2, 3, 6) d KB (A, B, x) = ∑ (0,1,4,5) JK Synthesis using JK F.F. 0 x 1 x x 1 0 x 1 x x 1 x 0 Example : Detect 3 or more consecutive 1’s

102
Example : Detect 3 or more consecutive 1’s D ESIGN OF C LOCKED S EQUENTIAL C IRCUITS WITH JK F.F. J A = B xK A = x’ J B = xK B = A’ + x’ JK Synthesis using JK Flip-Flops B 0010 Axxxx x B xxxx A1001 x B 01xx A01xx x B xx11 Axx01 x

103
Example : Detect 3 or more consecutive 1’s D ESIGN OF C LOCKED S EQUENTIAL C IRCUITS WITH T F.F. Present State Input Next State F.F. Input ABxABT A T B 00000 00101 01000 01110 10000 10111 11000 11111 0 0 0 1 1 0 1 0 T Synthesis using T Flip-Flops 0 1 1 1 0 1 1 0 T A (A, B, x) = ∑ (3, 4, 6) T B (A, B, x) = ∑ (1, 2, 3, 5, 6)

104
Example : Detect 3 or more consecutive 1’s D ESIGN OF C LOCKED S EQUENTIAL C IRCUITS WITH T F.F. T A = A x’ + A’ B x T B = A’ B + B x T Synthesis using T Flip-Flops B 0010 A1001 x B 0111 A0101 x

105
Example : 3-bit binary counter D ESIGN OF C LOCKED S EQUENTIAL C IRCUITS WITH T F.F.

107
Design a one-input, one-output serial 2's complementer. The circuit accepts a string of bits from the input and generates the 2's complement at the output. The circuit can be reset asynchronously to start and end the operation. D ESIGN OF C LOCKED S EQUENTIAL C IRCUITS WITH D F.F.

Similar presentations

OK

EE 5900 Advanced Algorithms for Robust VLSI CAD, Spring 2009 Sequential Circuits.

EE 5900 Advanced Algorithms for Robust VLSI CAD, Spring 2009 Sequential Circuits.

© 2017 SlidePlayer.com Inc.

All rights reserved.

Ads by Google

Ppt on x ray diffraction Ppt on solar based traffic light control system Download ppt on transportation and communication Ppt on types of web browser Ppt on role of water resources management Ppt on soil moisture sensor Ppt on home automation using rf Appt only ph clinics Ppt on different types of houses in india Ppt on french revolution download