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INTRODUCTION TO SEQUENCIAL CIRCUIT. I NTRODUCTION Combinational circuits: contain no memory elements the outputs depends on the current inputs Sequential.

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Presentation on theme: "INTRODUCTION TO SEQUENCIAL CIRCUIT. I NTRODUCTION Combinational circuits: contain no memory elements the outputs depends on the current inputs Sequential."— Presentation transcript:

1 INTRODUCTION TO SEQUENCIAL CIRCUIT

2 I NTRODUCTION Combinational circuits: contain no memory elements the outputs depends on the current inputs Sequential circuits: a feedback path outputs depends on present inputs and present states (pre. inputs) (inputs, current state)  (outputs, next state)

3 S EQUENTIAL C IRCUITS General model of a sequential logic circuit.

4 S EQUENTIAL C IRCUITS A sequential circuit is specified by a time sequence of inputs, outputs and internal states Sequential circuits must be able to remember the past history Flip-flops: most commonly used memory devices A function of - present inputs & - present state of memory elements (the past sequence of inputs)

5 S EQUENTIAL C IRCUIT --- W HY ? Iteration 1: A=0110 B=1100 Iteration 2: if (A

6 Synchronous clocked sequential circuit Use clock pulses generated by a clock generator C LOCK

7 T YPES OF S EQUENTIAL C IRCUITS Synchronous sequential circuits Storage elements are affected at discrete time instants Use clock pulses in the inputs of storage elements Asynchronous sequential circuits Storage elements are affected at any time instant depending on the timing of their signals

8 S YNCHRONOUS S EQUENTIAL C IRCUITS Storage elements are affected only with the arrival of each pulse The storage elements used in the clocked sequential circuits are called “flip-flops” Synchronous Use clock pulses in the inputs of storage elements

9 Synchronous sequential circuits a master-clock generator to generate a periodic train of clock pulses the clock pulses are distributed throughout the system clocked sequential circuits (most popular) no instability problems the memory elements: flip-flops binary cells capable of storing one bit of information two outputs: one for the normal value and one for the complement value maintain a binary state indefinitely until directed by an input signal to switch states S YNCHRONOUS S EQUENTIAL C IRCUITS

10 L ATCHES AND F LIP -F LOPS What is the difference? Flip-flops use a clock and are clock edge triggered When the clock edge occurs the data on the data inputs determines the next state of the flip-flop Latches are level sensitive Latches are very common in VLSI circuits 8/22/2012 – ECE 3561 Lect 2 Copyright Joanne DeGroat, ECE, OSU 10

11 T HE BASIS How do you design logic that holds state? Logic gates are feed forward devices who’s output depends on the value of the inputs So how to create a device that holds a state? Feedback!! 8/22/2012 – ECE 3561 Lect 2 Copyright Joanne DeGroat, ECE, OSU 11

12 L ATCH VS. F LIP -F LOP Latch positive-edge triggered negative-edge triggered Q D Q CLK

13 L ATCHES The most basic types of flip-flops operate with signal levels  latch All FFs are constructed from the latches introduced here A FF can maintain a binary state indefinitely until directed by an input signal to switch states Set=1  Q=1, Reset=1  Q=0 Two NOR gates

14 L ATCHES IF R=0 S= IF R=1 S= Step 1: red number Step 2: yellow number Step 3: green number Step 4: black number

15 L ATCHES After that, R=0 and S= Step 1: red number Step 2: yellow number Step 3: green number Step 4: black number  Q=0 Q ’ = … Wrong! IF R=1 S=

16 L ATCHES (S,R)= (0,0): no operation (S,R)=(0,1): reset (Q=0, the clear state) (S,R)=(1,0): set (Q=1, the set state) (S,R)=(1,1): indeterminate state (Q=Q'=0) Under normal condition, (S,R) = (0,0) Set (S,R)=(1,0) can store a 1 in it. Then the output maintains 1 even the input is set as (S,R)=(0,0) SR Q’ Q 00**// a stable state in the previous state 1001// change to another stable state “Set ” 0001// remain in the previous state 0110// change to another stable state “Reset ” 0010// remain in the previous state // oscillate (unpredictable) if next SR=00 the condition should be avoided Q  a memory/storage unit to store a bit (by setting different R and S) SR latch

17 SR L ATCH WITH NAND GATES (S ’ R ’ LATCH ) SR latch with NAND gates reset set (c) Graphic symbol S’R’ latch

18 SR L ATCH WITH C ONTROL I NPUT En=0, no change En=1, enable 0/1 S_ R_ 1/S' 1/R' The complement output of the previous R ’ S ’ latch.

19 T HE S ET -R ESET (SR) L ATCH The circuit has no memory Output depends not only on present inputs but the state of the latch when the current inputs were applied. The state 1 1 on the inputs not allowed. 8/22/2012 – ECE 3561 Lect 2 Copyright Joanne DeGroat, ECE, OSU 19

20 HDL CODE FOR SR L ATCH The core of the model --set up dataflow for SR latch Q <= R NOR Qbar AFTER 5 ns; Qbar <= S NOR Q AFTER 5 ns; Apply stimulus to S and R What does simulation show 8/22/2012 – ECE 3561 Lect 2 Copyright Joanne DeGroat, ECE, OSU 20

21 HDL SIMULATION OF SR LATCH 8/22/2012 – ECE 3561 Lect 2 21 Copyright Joanne DeGroat, ECE, OSU

22 T HE NEXT STATE The state 11 is not allowed S=1 Q to 1 R=1 Q to 0 S and R 00 Hold state 8/22/2012 – ECE 3561 Lect 2 22 Copyright Joanne DeGroat, ECE, OSU

23 N EXT STATE TRUTH TABLE From the table you can get the next state equation Here – Q + = S + R’Q An equation that expresses the state of a latch (or flip flop) in terms of its present state and inputs is referred to as the characteristic equation. 8/22/2012 – ECE 3561 Lect 2 23 Copyright Joanne DeGroat, ECE, OSU

24 eliminate the undesirable conditions of the indeterminate state in the RS flip-flop D: data D  Q when En=1; no change when En=0 S_ R_ 0/1 1/D' 1/D D Latch (Transparent Latch) Q D Q En level triggered (level-sensitive) When En=1, Q changes as soon as D changes

25 8/22/2012 – ECE 3561 Lect 2 25 T HE D L ATCH The D Latch is the most common element in CMOS design. Copyright Joanne DeGroat, ECE, OSU

26 8/22/2012 – ECE 3561 Lect 2 26 T IMING DIAGRAM FOR A D L ATCH Copyright Joanne DeGroat, ECE, OSU

27 8/22/2012 – ECE 3561 Lect 2 27 T HE D F/F The D Flip-Flop has edge triggered operation Can be positive edge triggered (as here) or negative edge triggered Copyright Joanne DeGroat, ECE, OSU

28 8/22/2012 – ECE 3561 Lect 2 28 T IMING FOR A D F LIP -F LOP Important to note relationships Copyright Joanne DeGroat, ECE, OSU

29 8/22/2012 – ECE 3561 Lect 2 29 D F/F B EHAVIOR Some important timing parameters Clock to output Setup and hold time Copyright Joanne DeGroat, ECE, OSU

30 8/22/2012 – ECE 3561 Lect 2 30 D F/F WITH P RESET AND C LEAR Can add preset and clear for easier circuit initialization. Copyright Joanne DeGroat, ECE, OSU

31 8/22/2012 – ECE 3561 Lect 2 31 S CAN C HAINS D F/F are the F/F used in scan chains. What are scan chains? Copyright Joanne DeGroat, ECE, OSU

32 8/22/2012 – ECE 3561 Lect 2 32 S CAN C HAINS Can use scan chains to inputs data or extract data Copyright Joanne DeGroat, ECE, OSU

33 8/22/2012 – ECE 3561 Lect 2 33 T HE T F LIP F LOP Toggle Flip Flop Copyright Joanne DeGroat, ECE, OSU

34 8/22/2012 – ECE 3561 Lect 2 34 M ORE ON B ASIC S EQUENTIAL E LEMENTS The S-R F/F Q*=S+R’Q The Toggle F/F Q*=Q’ Q* is next value or next state Copyright Joanne DeGroat, ECE, OSU

35 8/22/2012 – ECE 3561 Lect 2 35 D F/F AND J/K F/F D F/F Q* = D J/K F/F Q*=JQ’+K’Q Copyright Joanne DeGroat, ECE, OSU

36 F LIP -F LOPS A trigger The state of a latch or flip-flop is switched by a change of the control input Level triggered – latches Edge triggered – flip-flops Level triggered Edge triggered

37 P ROBLEM OF L ATCH If level-triggered flip-flops are used the feedback path may cause instability problem (since the time interval of logic-1 is too long) multiple transitions might happen during logic-1 level Edge-triggered flip-flops the state transition happens only at the edge eliminate the multiple-transition problem

38 E DGE -T RIGGERED D F LIP -F LOP Master-slave D flip-flop two separate latches a master latch (positive-level triggered) a slave latch (negative-level triggered) Two designs to solve the problem of latch: a.Master-slave D flip-flop b.Edge-trigger D flip-Flop o

39 Two D latches and one inverter The circuit samples D input and changes its output Q only at the negative-edge of CLK isolate the output of FF from being affected while its input is changing CLK=1, enabled CLK=0, disabled CLK=1, disabled CLK=0, enabled old value new value Old value is equal to the new value only at the instant of CLK’s falling edge positive-edge M ASTER - SLAVE D FLIP - FLOP

40 CP = 1: (S,R)  (Y,Y'); (Q,Q') holds CP = 0: (Y,Y') holds; (Y,Y')  (Q,Q') (S,R) could not affect (Q,Q') directly the state changes coincide with the negative-edge transition of CP

41 Edge-Triggered Flip-Flops the state changes during a clock-pulse transition A D-type positive-edge-triggered flip-flop  three SR latches SR latch with NAND gate

42 (S,R) = (0,1): Q = 1 (S,R) = (1,0): Q = 0 (S,R) = (1,1): no operation (S,R) = (0,0): should be avoided Edge-Triggered Flip-Flops If Clk=1 and D =0  R =0  Reset. Output Q is 0. Then, if D changes to 1, R remains at 0 and Q is 0. If Clk=0  S=1 and R=1  no operation. Output Q remains in the present state 01

43 (S,R) = (0,1): Q = 1 (S,R) = (1,0): Q = 0 (S,R) = (1,1): no operation (S,R) = (0,0): should be avoided Edge-Triggered Flip-Flops Then, Clk=0  S =1, R =1  no operation (Q=0) Then, if Clk=1 and D =1  S =0  Set. Output Q is 1. (see the blue dot-line flow) Then, if D changes to 0, S remains at 0 and Q =1; If Clk=0  S=1 and R=1  no operation. Output Q remains in the present state (old) (new) If Clk=1 and D =0  R =0  Reset. Output Q is 0. Then, if D changes to 1, R remains at 0 and Q is 0.

44 P OSITIVE -E DGE -T RIGGERED F LIP -F LOPS Summary Clk=0: (S,R) = (1,1), no state change Clk=  : state change once Clk=1: state holds eliminate the feedback problems in sequential circuits All flip-flops must make their transition at the same time


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