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1 CURSO: PRINCIPIOS ELECTRICOS Y APLICACIONES DIGITALES © ILCEO: ING. MIGUEL ANGEL PEREZ SOLANO INSTRUCTOR: MIGUEL ANGEL PEREZ SOLANO Ingeniero en Comunicaciones.

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Presentation on theme: "1 CURSO: PRINCIPIOS ELECTRICOS Y APLICACIONES DIGITALES © ILCEO: ING. MIGUEL ANGEL PEREZ SOLANO INSTRUCTOR: MIGUEL ANGEL PEREZ SOLANO Ingeniero en Comunicaciones."— Presentation transcript:

1 1 CURSO: PRINCIPIOS ELECTRICOS Y APLICACIONES DIGITALES © ILCEO: ING. MIGUEL ANGEL PEREZ SOLANO INSTRUCTOR: MIGUEL ANGEL PEREZ SOLANO Ingeniero en Comunicaciones y Electrónica Instituto Tecnológico de Oaxaca UNIDAD 2: ELECTRONICA DIGITAL

2 2 ANTECEDENTES CONCEPTUALES Estados Lógicos: Niveles de una señal digital; 0(cero) y 1(uno) BIT: Digito binario (BInary digiT) Niveles Lógicos: Niveles de voltaje asignados a cada estado lógico NIBBLE; Agrupación de 4 bits BYTE: Agrupación de 8 bits. WORD: Agrupacion de bits determinado por las diferentes tecnologías. SISTEMAS NUMERICOS; DECIMAL, HEXADECIMAL, BINARIO ARITMETICA BINARIA; Suma, resta, multiplicacion, division

3 3 2.1 Tablas de verdad y compuertas lógicas TABLA DE VERDAD: Es un método tabular que representa el comportamiento funcional de una compuerta o un circuito lógico COMPUERTA LOGICA: Circuito Digital que realiza una operación lógica. Existen 3 operaciones básicas; AND, OR y NOT, además de 4 provenientes de ellas; NAND, NOR, XOR y XNOR.

4 NOT, OR y AND

5 Otras (NOR, NAND, XOR, etc.).

6 Expresiones booleanas Las expresiones booleanas se usan para determinar si un conjunto de una o más condiciones es verdadero o falso, y el resultado de su evaluación es un valor de verdad. Los operandos de una expresión booleana pueden ser cualquiera de los siguientes: Los operandos de una expresión booleana pueden combinarse con los operadores siguientes: NOT (NO) Este operador produce el valor Verdadero, si su operando es Falso; y el valor Falso, si su operando es Verdadero AND (Y) Este operador produce el valor Verdadero si ambos operandos son Verdadero. Si cualquiera de los dos operandos es Falso, entonces el resultado será Falso; OR (O) Este operador realiza una operación OR-inclusiva. El resultado es Verdadero si cualquiera de los dos operandos, o ambos son Verdadero. En caso contrario, es Falso.

7 7 2.2 Diseño de circuitos combinacionales.

8 Metodología de diseño Una vez que se tiene la idea 1.- Establecer la variables mediante un diagrama a bloques 2..- Crear su tabla de verdad 3.- Simplificación (minimización) utilizando método; algebra Booleana, mapas de karnaugh o Método de Quine McCluskey 4.- Simulación 5.- Implementación

9 Minitérminos y maxitérminos.. Y= A’B’C + ABC’ +ABC’+ABC Y = (A+B’+C’)(A+B+C)(A’+B+C)

10 Técnicas de simplificación Por algebra de Boole Por el método de Mapas de Karnaugh Por el método de Queen McCluskey

11 Teoremas y postulados del algebra de Boole Ley Asociativa A+B+C = A+(B+C) = (A+B)+C Ley Conmutativa A+B+C = C+B+A Ley Distributiva A(B+C)= AB + AC Reglas del algebra booleana Teoremas de D’morgan

12 Mapas Karnaugh Un mapa de Karnaugh es una representación gráfica de la tabla de verdad La tabla de verdad tiene un renglón por cada minitérmino El mapa de Karnaugh tiene una celda por cada minitérmino

13 Ejemplos 13

14 Implementación y aplicación de circuitos combinacionales. Un circuito combinacional se caracteriza por que su valor de salida solo depende de sus valores de entrada. PLDs CPLDs FPGA´s Para simulación: Proteus y diseño en FPGAs IseWeb pack 14.7

15 Lógica secuencial Previously, we have considered combinational circuits where the output values depend only on the values of signals applied to the inputs Another class of logic circuits have the property that the outputs depend not only on the current inputs, but also on the past behavior of the circuit. Such circuits include storage elements that store the values of logic signals. SEQUENTIAL CIRCUITS

16 16 Previously, we have considered combinational circuits where the output values depend only on the values of signals applied to the inputs Another class of logic circuits have the property that the outputs depend not only on the current inputs, but also on the past behavior of the circuit. Such circuits include storage elements that store the values of logic signals. STORAGE ELEMENTS SEQUENTIAL CIRCUITS Contents of the storage elements represent the state of the circuit Input value changes may leave the circuit in the same state or cause it to change to a new state Over time, the circuit changes through a sequence of states as a result of changes in the inputs Circuits that exhibit this behavior are referred to as sequential circuits

17 17 Sequential circuits usually contain combinational subcircuits and feedback paths.

18 18 A similar circuit, constructed with NOR gates can also be constructed Inputs, Set and Reset, provide the means to changing the state, Q, of the circuit This circuit is referred to as a basic latch BASIC SR LATCH When R=S=0 the circuit remains in its current state (either Qa=1 and Qb=0 or Qa=0 and Qb=1). When S=1 and R=0, the latch is set into a state where Qa=1 and Qb=0 When S=0 and R=1, the latch is reset into a state where Qa=0 and Qb=1 Where S=1 and R=1, Qa=Qb=0 (there are actually problems with this state as we will see)

19 19

20 20 Basic SR latch timing diagram

21 21 The basic SR latch changes its state whenever its inputs change It may be desirable to add an enable signal to the basic SR latch that allows us to control when the circuit can change states Such a circuit is referred to as a gated SR latch GATED SR LATCH

22 22

23 23 GATED SR LATCH TIMING DIAGRAM GATED SR LATCH WITH NAND GATES

24 24 Another useful latch has a single data input, D, and it stores the value of this input under the control of a clock signal This is referred to as a gated D latch – Useful in circuits where we want to store some value – The output of an adder/subtractor circuit would be one example GATED D LATCH

25 25 GATED D LATCH

26 26 Since the output of the D latch is controlled by the level (0 or 1) of the clock input, the latch is said to be level sensitive – All of the latches we have seen have been level sensitive It is possible to design a storage element for which the output only changes a the point in time when the clock changes from one value to another Such circuits are said to be edge triggered LEVEL VERSUS EDGE SENSITIVITY

27 27 Previously we have ignored the effects of propagation delay. In practical circuits, it is essential to account for these delays For the gated D latch (and others as well), it is important that the value of D not change at the time the clock (clk) goes from 1 to 0 – The designer must make sure the signal is stable when the critical change in the clock takes place The minimum time the D signal must remain stable prior to the negative edge (1->0) of the clock signal is called the setup time (tsu) The minimum time the D signal must remain stable after the negative edge of clock is the hold time (th) – Typical CMOS values are: tsu=3ns and th=2ns EFFECTS OF PROPAGATION DELAYS

28 28 SETUP AND HOLD TIMES

29 29 The gated latch circuits presented are level sensitive and can change states more than once during the ‘active’ period of the clock signal Circuits (storage elements) that can change their state no more than once during a clock period are also useful Two types of circuits with such behavior – Master-slave flip-flip – Edge-triggered flip-flop FLIP-FLOPS

30 30 Consists of 2 gated D latches: – The first, master, changes its state while clock=1 – The second, slave, changes its state while clock=0 MASTER-SLAVE D FLIP-FLOP

31 31 When clock=1, the master tracks the values of the D input signal and the slave does not change – Thus Qm follows any changes in D and Qs remains constant When the clock signal changes to 0, the master stage stops following the changes in the D input signal At the same time, the slave stage responds to the value of Qm and changes states accordingly Since Qm does not change when clock=0, the slave stage undergoes at most one change of state during a clock cycle From an output point of view, the circuit changes Qs (its output) at the negative edge of the clock signal MASTER-SLAVE D FLIP-FLOP

32 32 MASTER-SLAVE D FLIP-FLOP

33 33 A circuit, similar in functionality to the master-slave D flip-flop, can be constructed with 6 NAND gates EDGE-TRIGGERED FLIP-FLOP

34 34 The previous circuit responds on the positive edge of the clock signal A negative-edge triggered D flip-flop can be constructed by replacing the NAND with NOR gates EDGE-TRIGGERED FLIP-FLOP

35 35 COMPARING D STORAGE ELEMENTS

36 36 CLEAR AND PRESET INPUTS It may be desirable to specifically set (Q=1) or clear (Q=0) a flip-flop Practical flip-flops often have preset and clear inputs – Generally, these inputs are asynchronous (they do not depend on the clock signal)

37 37 Another flip-flop type, the T flip-flop, can be derived from the basic D flip-flop presented Feedback connections make the input signal D equal to the value of Q or Q’ under control of a signal labeled T T FLIP-FLOP

38 38 The name T derives from the behavior of the circuit, which ‘toggles’ its state when T=1 – This feature makes the T flip-flop a useful element when constructing counter circuits T FLIP-FLOP

39 39 The JK flip-flop can also be derived from the basic D flip-flop such that D=JQ’+K’Q The JK flip-flop combines aspects of the SR and the T flip-flop – It behaves as the SR flip-flop (where J=S andK=R) for all values except J=K=1 – For J=K=1, it toggles like the T flip-flop JK FLIP-FLOP

40 40 JK flip-flop timing diagram

41 41 A flip-flop stores one bit of information. When a set of n flip-flops is used to store n bits of data, we refer to these flip-flops as a register – Common register usages include Holding a data value output from an arithmetic circuit Holding a count value in a counter circuit A common clock signal is typically used for each flip-flop in a register REGISTERS

42 42 A register that provides the ability to shift its contents by a single bit – May be to the right or left (or possibly both) SHIFT REGISTER

43 43 Data is shifted to the right in a serial fashion using the In input Positive edge triggered – Contents of each flip-flop are transferred to the next flip-flop at each positive edge of the clock Level sensitive devices would not be appropriate for this circuit SHIFT RIGHT REGISTER

44 44 Data transfer in computer systems is a common function – If the transfer is n-bits at a time, the transfer is said to be in parallel – If the transfer is 1-bit at a time, the transfer is said to be serial To transfer data serially, data is loaded into a register in parallel (in one clock cycle) and then shifted out one bit at a time – Parallel-to-serial data conversion If bits are received serially, after n clock cycles the contents of a register can be accessed in parallel as an n-bit item – Serial-to-parallel conversion PARALLEL-ACCESS SHIFT REGISTER

45 45 PARALLEL-ACCESS SHIFT REGISTER

46 46 Special purpose arithmetic circuits used for the purpose of counting – Design circuits that can increment or decrement a count by 1 Counter circuits server many purposes – Count occurrences of certain events – Generate timing intervals for controlling various tasks in a digital system – Track elapsed time between events Often (but not always) built with T flip-flops because the toggle feature is naturally suited for implementing the counting operation COUNTERS

47 47 UP-COUNTER WITH T FLIP-FLOPS

48 48 DOWN COUNTER WITH T FLIP-FLOPS

49 49 The previous counters are examples of asynchronous counters. Also called ripple counters. – Input clock is only connected to one flip-flop – Clocks for other flip-flops are (or are derived from) the outputs of the previous flip-flops This form of counter is slow because the cascaded clocking scheme – The clock source ripples from stage-to-stage – The ripple effect is similar to that of a ripple carry adder circuit ASYNCHRONOUS COUNTERS

50 50 Synchronous counters are built by clocking all the flip-flops at the same time (with a single clocking source) – Faster response than asynchronous counters Synchronous counters with T flip-flops – Least significant bit, Q0, changes every clock cycle – Bit one, Q1, only changes when Q0=1 – Bit two, Q2, only changes when Q0=Q1=1 SYNCHRONOUS COUNTERS

51 51 T FLIP-FLOP SYNCHRONOUS COUNTER

52 52 It may be desirable to disable counting or clear the counter – Include an enable control signal – Use a flip-flop with asynchronous clear capability ENABLE AND CLEAR CAPABILITY

53 53 A 4-bit up counter counts in the sequence 0,1,2,…,15,0,1… The count is given by the flip-flop outputs Q3Q2Q1Q0 The D inputs are given by: D0=Q0 ⊕ Enable D1=Q1 ⊕ Q0 ⋅ Enable D2= Q2 ⊕ Q1 ⋅ Q0 ⋅ Enable D3= Q3 ⊕ Q2 ⋅ Q1 ⋅ Q0 ⋅ Enable D FLIP-FLOP SYNCHRONOUS COUNTER

54 54 FOUR-BIT COUNTER (D FLIP-FLOPS)

55 55 It is common for counters to begin a count with a zero value – An asynchronous clear input can be used for his purpose It may be desirable for a counter to begin with a non-zero value Adding circuitry to provide parallel load capability is necessary A control input, load, is used to select a mode of operation – Load=0, circuit counts – Load=1, parallel load a new value into the counter COUNTERS WITH PARALLEL LOAD

56 56 PARALLEL LOAD COUNTER

57 57 Circuits where a clock signal is used to control operation are called synchronous sequential circuits – The term active clock edge refers to the clock edge that causes a change in state (positive or negative) Realized using combinational logic and one or more flip-flops Two models for synchronous sequential circuits – Moore model: circuit outputs depend only on the present state of the circuit – Mealy model: circuit outputs depend on the present state of the circuit and the primary inputs Sequential circuits are also called finite state machines (FSM) SYNCHRONOUS SEQUENTIAL CIRCUITS

58 58 MOORE VERSUS MEALY MACHINES

59 59 We will introduce techniques for sequential circuit design via a simple example Design a circuit that meets the following specifications: – The circuit has one input, w, and one output, z – All changes in the circuit occur on the positive edge of the clock signal – Output z=1 if the input w was 1 during the two immediately preceding clock cycles From this specification it is obvious that z cannot depend solely of the value of w BASIC DESIGN STEPS

60 60 The example input and output sequence below aides in the description of the circuit SEQUENCES OF SIGNALS The first step in designing an FSM is determining how many states are needed and which transitions are possible from onestate to another – No preset procedure for this – The designer must think about what the circuit is to accomplish A good beginning is to define a reset state that the circuit should enter when power is applied or when a reset signal is received STATE DIAGRAM

61 61 For our example, assume the starting state is called A As long as w=0, the circuit should do nothing and z=0 STATE DIAGRAM When w=1, the circuit should ‘remember’ this by transitioning to a new state (B) This transition should occur at the next positive edge of the clock signal

62 62 When in state B and w=1, the circuit should remember’ this by transitioning to a new‘state (C) STATE DIAGRAM COMPLETE STATE DIAGRAM Moore model state diagram

63 63 A state diagram describes circuit functionality, but does not describe circuit implementation Translation to a tabular form is necessary The state table should contain – All transitions from each present state to each next state for all valuations of the input signals – The output, z, is specified with respect to the present state STATE TABLE

64 64 The states are defined in terms of variables (A, B, and C) Each state is represented by a particular valuation of state variables Each state variable is implemented with a flip-flop Since three states have to be realized, it is sufficient to use two state variables – Use y2y1 for the present state (present state variables) – Use Y2Y1 for the next state (next state variables) STATE ASSIGNMENT

65 65 STATE-ASSIGNED TABLE Note the addition of the y2y1=11 state. Although it is not used, it is needed for completeness.

66 66 K-maps are constructed from the state table for: – Circuit outputs (z in this case) – Inputs for the flip-flops (next-state K-maps) Constructing the next-state maps depends on the type of flip-flop (D, T, JK) used for theimplementation – D is the most straightforward: next-state mapsare constructed directly from the state table since Q(t+1)=Q+=D – T and JK implementations will be covered later NEXT-STATE AND OUTPUT MAPS

67 67 STATE TABLE AND NEXT-STATE MAPS

68 68 STATE TABLE AND OUTPUT MAP

69 69 CIRCUIT DIAGRAM

70 70 TIMING DIAGRAM

71 71 Design a 2-bit counter that counts – in the sequence 0,1,2,3,0,… if a given control signal U=1, or – in the sequence 0,3,2,1,0,… if a given control signal U=0 This represents a 2-bit binary up/down counter – An input U to control to count direction – A RESET input to reset the counter to the value zero – Two outputs (Z1 Z0) representing the output (0-3) – Counter counts on positive edge transitions of a common clock signal Design this counter as a synchronous sequential machine using – D-type, T-type, JK-type flip-flops COUNTER DESIGN EXAMPLE

72 72 COUNTER STATE DIAGRAMCOUNTER STATE TABLE

73 73 Choosing a state assignment of A=00, B=01, C=10 and D=11 makes sense here because the outputs Z1Z0 become the outputs from the flip- flops directly STATE-ASSIGNED STATE TABLE

74 74 When D flip-flops are used to implement an FSM, the next-state entries in the stateassigned state table correspond directly tothe signals that must be applied to the D inputs Thus, K-maps for the D inputs can be derived directly from the state- assigned state table This will not be the case for the other types of flip-flops (T, JK) D-TYPE FLIP-FLOP IMPLEMENTATION

75 75 STATE TABLE AND NEXT-STATE MAPS

76 76 CIRCUIT DIAGRAM (D FLIP-FLOP)

77 77 For the T- or JK-type flip-flops, we must derive the desired inputs to the flip-flops Begin by constructing a transition table for the flip-flop type you wish to use – This table simply lists required inputs for a given change of state The transition table is used with the stateassigned state table to construct an excitation table – The excitation table lists the required flip-flop inputs that must be ‘excited’ to cause a transition to the next state DESIGN USING OTHER FLIP-FLOP TYPES

78 78 TRANSITION TABLES

79 79 T-TYPE FLIP-FLOP IMPLEMENTATION

80 80 EXCITATION TABLE AND K-MAPS

81 81 CIRCUIT DIAGRAM (T FLIP-FLOP )

82 82 JK-TYPE FLIP-FLOP IMPLEMENTATION Use entries from the transition table to derive the flip-flop inputs based on the state-assigned state table – This must be done for each input (J and K) on each flip-flop

83 83 JK-TYPE FLIP-FLOP IMPLEMENTATION

84 84 EXCITATION TABLE AND K-MAPS

85 85 EXCITATION TABLE AND K-MAPS

86 86 CIRCUIT DIAGRAM (JK FLIP-FLOP)

87 87 1. States that have the same next state for a given input should be given adjacent assignments 2. States that are the next state of the same state should be given adjacent assignments. STATE ASSIGNMENT GUIDELINES Keep the following in mind: 1. Assign the starting state to the ‘0’ cell on the map (i.e. the starting state has all flip-flop outputs=0) 2. Satisfy guideline 1 and multiple occurrences of guideline 2 first 3. If the guidelines require that 3 or 4 states be adjacent, place these states within a group of 4 adjacent squares on the map 4. Guideline 3 is less important than 1 or 2 unlessthe circuit is to have multiple outputs

88 88 EXAMPLE MOORE STATE DIAGRAM

89 89 EXAMPLE STATE ASSIGNMENT

90 90 Mealy model: circuit outputs depend on the present state of the circuit and the primary inputs, giving additional flexibility in designing sequential circuits Greater flexibility often leads to simpler circuits MEALY STATE MODEL

91 91 For the Mealy model, outputs are no longer associated with a particular state – Outputs are associated with transitions between states Typical Mealy model state diagram – Detects w=11 sequence MEALY STATE DIAGRAM

92 92 The state table for a Mealy model FSM differs from the Moore model FSM only in how theoutputs are viewed MEALY MODEL STATE TABLE

93 93 STATE-ASSIGNED STATE TABLE Design example Construct a Mealy state diagram for a sequence detector that detects the input sequence w=101

94 94 NOTAS DEL CURSO


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