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D YNAMIC S YNCHRONIZER F LIP -F LOP P ERFORMANCE IN F IN FET T ECHNOLOGIES NOCS 2014 Mark Buckler 1, Arpan Vaidya 2, Xiaobin Liu 2, Wayne Burleson 2,3.

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Presentation on theme: "D YNAMIC S YNCHRONIZER F LIP -F LOP P ERFORMANCE IN F IN FET T ECHNOLOGIES NOCS 2014 Mark Buckler 1, Arpan Vaidya 2, Xiaobin Liu 2, Wayne Burleson 2,3."— Presentation transcript:

1 D YNAMIC S YNCHRONIZER F LIP -F LOP P ERFORMANCE IN F IN FET T ECHNOLOGIES NOCS 2014 Mark Buckler 1, Arpan Vaidya 2, Xiaobin Liu 2, Wayne Burleson 2,3 Cornell University 1, University of Mass. Amherst 2, AMD Research 3 September 18, 2014

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3 W HY ARE WE LOOKING AT S YNCHRONIZERS ?  Low power NoCs utilize fine grain DVFS  Leads to Inter Clock- Domain Communication Requires synchronizers! Error rates similar to that of transient faults Page 2 of 35 Motivation Flip-Flop Evaluation The Dynamic Synchronizer Conclusions

4 P ROBLEM : M ETASTABILITY Page 3 of 35 Motivation Flip-Flop Evaluation The Dynamic Synchronizer Conclusions

5 T HE B RUTE -F ORCE S YNCHRONIZER Page 4 of 35 Motivation Flip-Flop Evaluation The Dynamic Synchronizer Conclusions  Synchronizer reliability is quantified as the Mean Time Between Failures (MTBF)

6 S YNCHRONIZER F LIP -F LOP E VALUATION  τ is the strongest circuit level term in calculating MTBF  Goal 1: Provide NoC designers with τ simulations over design parameters  Goal 2: Find the best Flip-Flops, and ensure that they can be used by NoC designers Page 5 of 35 Motivation Flip-Flop Evaluation The Dynamic Synchronizer Conclusions

7 S YNCHRONIZER F LIP -F LOP E VALUATION  Flip-Flops: PowerPC Flip-Flop Dynamic Latch Flip-Flop Psuedo-NMOS Flip-Flop  Technology Nodes Planar (50nm and 22nm) FinFET (20nm, 10nm and 7nm) Page 6 of 35 Motivation Flip-Flop Evaluation The Dynamic Synchronizer Conclusions

8 S IMULATION T ECHNIQUE Page 7 of 35 Motivation Flip-Flop Evaluation The Dynamic Synchronizer Conclusions Zhou and Ashouei et al, Microelectronics Journal, 2011

9 E FFECT OF TECHNOLOGY CHANGE Page 8 of 35 DLFF Power PC PseudoNMOS Motivation Flip-Flop Evaluation The Dynamic Synchronizer Conclusions

10 V OLTAGE AND T EMPERATURE S ENSITIVITY Page 9 of 35 Motivation Flip-Flop Evaluation The Dynamic Synchronizer Conclusions PseudoNMOS in 22nm DLFF in 22nm

11 V OLTAGE AND T EMPERATURE S ENSITIVITY Page 10 of 35 Motivation Flip-Flop Evaluation The Dynamic Synchronizer Conclusions PseudoNMOS in 20nm DLFF in 20nm  FinFETs are more sensitive to changes in threshold voltage from lower temperatures

12 E FFECT OF F ORWARD -B ODY B IASING Page 11 of 35 Motivation Flip-Flop Evaluation The Dynamic Synchronizer Conclusions  DLFF is best for high voltage, but we may have a problem... 20nm (FinFET) 22nm (Planar)

13 T HE D YNAMIC L ATCH F LIP -F LOP  A reset signal is necessary… Page 12 of 35 Motivation Flip-Flop Evaluation The Dynamic Synchronizer Conclusions Dike and Burton, IEEE SSC 1999

14 T HE D YNAMIC S YNCHRONIZER Page 13 of 35 Motivation Flip-Flop Evaluation The Dynamic Synchronizer Conclusions

15 T HE D YNAMIC S YNCHRONIZER Page 14 of 35 Motivation Flip-Flop Evaluation The Dynamic Synchronizer Conclusions

16 T HE D YNAMIC S YNCHRONIZER Page 15 of 35 Motivation Flip-Flop Evaluation The Dynamic Synchronizer Conclusions

17 B ENEFITS OF THE D YNAMIC S YNCHRONIZER  The Dynamic Synchronizer allows DLFFs to be used in typical synchronous systems  Improves the latency-reliability tradeoff! MTBF of 5,000 yrs over 5 yrs (same # of stages) or Latency of 2 cycles over 3 cycles (same MTBF) Page 16 of 35 Motivation Flip-Flop Evaluation The Dynamic Synchronizer Conclusions

18 C ONCLUSIONS  Evaluated synchronizer τ values τ continues to track with FO4 in FinFET FinFET increases sensitivity to temperature Body biasing still works for high voltage  The Dynamic Synchronizer We improved the latency-reliability tradeoff by enabling the use of low τ flip-flops Page 17 of 35 Motivation Flip-Flop Evaluation The Dynamic Synchronizer Conclusions


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