Presentation on theme: "Reading Assignment: Rabaey: Chapter 7"— Presentation transcript:
1 Reading Assignment: Rabaey: Chapter 7 ELEC 516 VLSI System Design and Design Automation Spring Lecture 5: Flip-Flop/Latch DesignReading Assignment:Rabaey: Chapter 7Note: some of the figures in this slide set are adapted from the slide setof “ Digital Integrated Circuits” by Rabaey et. al., Copyright 2002
2 Motivations: Why do we need sequential circuits? Need memoryPipeline the system so that new operations start before the old ones complete.Add registers to keep operations separate.Convert parallel operations to a sequence of serial operations (faster operations per cycle/ smaller).Need to process a sequence of inputs and want to reuse the same hardware (Finite State Machine)
3 Sequential Logic Memory Element: FsLOGICtp,combfInOutMemory Element:Stores a value as controlled by clock.May have load signal, etc2 storage mechanismspositive feedbackcharge-based
4 Memory Elements - Latches and flip-flops A generic memory element has an internal memory and some circuitry to control access to the internal memory. which is controlled by the clock input.Memory element differ in many key respect:exactly what form of clock signal causes the input data value to be read;how the behavior of data around the read signal from clock affects the stored value;when the stored value is presented to the output;whether there is a combinational path from the input to the output.2 types of memory: latches and edge-triggered flip floplatches - transparent while the internal memory is being set from the data inputedge-triggered flip-flops (or register) - not transparent, reading the input value and changing the flip-flop’s output are two separate events.
5 Simple Circuit with Feedback One inverter with feedbackSelf-oscillation, 2 gate delays for one periodOdd-number of inverters with feedbackself-oscillation of 2x gate delays of one pathTwo inverters with feedbackMemory element (or states)Basis for commercial static RAM designsRead-only, but has no write functionMemory with read/write capabilitySelectively break the feedback path by transmission gates to load new value into the cellA can be written to Z when LD = 1Write SW On & Feedback SW OffZ holds the value when LD = 0Write SW Off & Feedback SW On“0?""1""0""1"ZLDLD’A
6 Latch versus Register Latch stores data when clock is low D Q D Q Clk stores data when clock risesDQDQClkClkClkClkDDQQ
7 Let’s build a latch Latches are multiplexers controlled by a clock: When CLK is high data will pass through otherwise the data is saved or kept unchanged feedback from output to inputCan be realized using transmission gates
8 Dynamic latch Stores charge on inverter gate capacitance: Uses complementary transmission gate to ensure that storage node is always strongly driven.Latch is transparent when transmission gate is closed.Storage capacitance comes primarily from inverter gate capacitance.Setup and hold times determined by transmission gate—must ensure that value stored on transmission gate is solid.
9 Dynamic latch- Stored charge leakage Stored charge leaks away due to reverse-bias leakage current.Stored value is good for about 1 ms.Value must be rewritten to be valid.If not loaded every cycle, must ensure that latch is loaded often enough to keep data valid.
10 Non-dynamic latches Must use feedback to restore value. Some latches are static on one phase (pseudo-static)—load on one phase, activate feedback on other phase.Example - Recirculating latch: Static on one phase:
11 Latch-Based Design N latch is transparent when f = 0 P latch is transparent when f = 1fNPLogicLatchLatchLogic
12 Positive Feedback: Bi-Stability The circuit presents only three operation pointsWhen the gain of the inverter in the transient region is larger than 1, A and B are the only stable operation points & C is a metastable operation point.
13 Meta-Stability Gain should be larger than 1 in the transition region C is an instable operating point. Every deviation (even small) causes the operation to run away (because of high gain).A and B are very stable operation points, the loop gain is much smaller than unity, eve a large deviation will not cause deviation from these operation points.
14 Flip states in Bistable Circuit Two different approaches:Cutting the feedback loopOpen the loop and write dataMultiplexer basedQ = Clk’.Q + Clk.InOverpowering the feedback loopApplying a trigger signal at the input of the flip-flop to overpower the stored value to a new valueCareful sizing of the transistors in the feedback loop and the input is necessary
15 Writing into a Static Latch Use the clock as a decoupling signal, that distinguishes between the transparent and opaque statesDCLKForcing the state(can implement as NMOS-only)Converting into a MUX
16 Other styles Small and lower clock load but sizing problems Very good style(Skew considerations)Fast and energy efficientPresents the lowestclock load
17 Mux-Based LatchPositive level latch. When the D path is ON, the feedback is cut-offNo sizing issues for correct operation.The number of transistors that the clock drives is an issue (clock has an activity factor of 1: CLK Load of four transistors.
23 The setup time raceSetup represents the race for new data to propagate around the feedback loop before clock closed the input gate.If data arrives too close to clock edge, it will not set up the feedback loop before clock closed the input TG
24 The hold time raceHold time represents the race for clock to close the input gate before next cycle’s data disturbs the stored valueIf data changes too soon after the clock edge, clock might not had time to switch off the input gate and new data will corrupt feedback loop
26 Maximum Clock Frequency Also:tcdreg + tcdlogic > tholdtcd: contamination delay = minimum delaytclk-Q + tp,comb + tsetup = TModern high performance systems are characterized by low logic depthThe register’s delay becomes very important as the registers because itaccounts for both the setup and propagation delay.DEC Alpha up has a max logic depth of 12 gates, &15% of the delaycorresponds to the register overhead.
28 Clock Overlap Problem Potential problems: XCLKCLKQADB(a) Schematic diagramCLKCLKPotential problems:Race condition: data at the output change at the rising edge of the clockNode A can be driven by both D and B when clock overlapCLKCLK(b) Overlapping clock pairsVariations in the routing wiresUsed to route CLK & CLK’Variations on the loadInverter’s delay
31 Dynamic Latches and registers Disadvantage of static FF - complexity, larger sizeThe requirement that the memory should hold state for extended periods of time can be relaxed in computational structureDynamic - use the charge stored in capacitance to eliminate the use of inverter pair to latch data: Pseudo-static latch (Charge-Based Storage)ADClkClk’BQClk=1: The input data is sampled on storage node A, during this time the slave is on hold mode, node B at high impedance.On the falling edge of the clock, T2 turns ON and the value sampled on A propagates to the output.Setup time is the delay of the transmission gateHold time is zero since the TG is turned off on the clock edge.Tc2q= delay of two inverters and a transmission gate.
32 Making a Dynamic Latch Pseudo-Static Fully dynamic circuit presents a number of drawbacks:Capacitive coupling can inject significant noise to the internal storage node.Leakage current: Most modern processors require that the clock can be slowed down or completely halted to conserve power in low activity periodsMost of these problems can be addressed by adding a weak feedback inverter Pseudo-Static LatchSlight cost in delay and silicon area.Improves noise immunity significantlyDynamic latches should be made Pseudo-Static, keep for very special cases of highly controlled environment (full-custom, high performance data path design)
33 Impact of non-overlapping clocks DClkClk’BQT1T2clkDuring the (0,0) overlap, PMOS of T1 and PMOS of T2 are ON, creating a direct path from D to Q.The same problem appears during the (1,1) overlap.clk(0,0)Overlap(1,1)OverlapOverlapping Clocks Can CauseRace ConditionsUndefined Signals
34 Flip-flop insensitive to clock overlap DDDDM2M6fM4fM8XInDCCfM3L1fM7L2M1M5f-sectionf-sectionC2MOS LATCH
35 C2MOS avoids Race Conditions In1M32675VDD48(a) (1-1) overlap(b) (0-0) overlapXDuring the (0,0) overlap, new data sampled on the falling edge of the clockwill not appear at D output.Same remark applied during the (1,1) overlap.
36 Operation of the C2MOS latch When f = 1, M3 and M4 are on, the 1st section is in the evaluation mode and the second section is in a hold mode (high impedance). M7 and M8 are off, decoupling the output from the input. The input D retains its previous value stored on the output capacitance.When f = 0, the first section is in hold mode and the second section is in evaluation mode, the value stored in CL1 propagates to the output node.A C2MOS register with (f - f ) clocking is insensitive to overlap, as long as rise and fall times of the clock edges are sufficiently small.
37 Dual Edge registersDual Edge registers are very interesting as they permit to run the Clock 2 times slower lower power on the clock node.DfN1XN2QY
38 Pipelined Logic using C2MOS FOutfVDDfVDDNORA CMOSGCCC123What are the constraints on F and G?No-race rule: A C2MOS-based pipelined circuit is race-free as long as the logic function F (static logic) between the latches are non-inverting
39 ExamplefVDDVDDf1fNumber of a static inversions should be even
40 Doubled C2MOS Latches-True single-phase clock register fVDDOutVVDDDDInInffOutDoubled n-C2 MOS latch(transparent when CLK= 1)Doubled p-C2 MOS latch(transparent when CLK= 0)+ Requires a single clock to build a positive & negative clock- Can suffer from charge sharing & noise pbs when clk low.
42 Example of Including Logic in TSPC CLKVDDQIn12Embedding logic into the latch reduces the delay overhead of the latch.This approach of embedding logic into the latch was extensively used in many high performance microprocessors including EV4 DEC Alpha.AND latch
43 Master-Slave Flip-flops DDDfVDDDfVDDDfVDDDYXD(a) Positive edge-triggered D flip-flop(b) Negative edge-triggeredD flip flop(c) Positive edge-triggered D flip-flopusing split-output latches
44 Pulse-Triggered Latches An Alternative Approach Ways to design an edge-triggered sequential cell:IDEA: construct a short pulse around the rising (or falling)edge of the clock. This would be the NEW clock input.Hold time is equal to the length of the pulse.Master-Slave LatchesPulse-Triggered LatchL1L2LDataDataDQDQDQClkClkClkClkClk+ Reduced clock load, small number of transistors required.+ Glitch circuitry can be shared by multiple register.- increase in verification complexity: Need to make sure the glitchIs properly generated!!!!!
45 Pulsed LatchesGlitch correspondsto the delay of theAND + 2 Inv
46 Pulsed Latches Hybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 : When the clock is low: M3 and M6 are off and P1 is ON. Node X is precharged to VDD, and the output is decoupled from X (Memory).CLKD’ is a delayed-inverted version of CLK. On the rising edge of the clock, M3 and M6 turn ON while M1 and M4 stay ON for a short period, and hence the latch is transparent and D is sampled. Once CLKD’ goes low node X is decoupled from D.
47 Hybrid Latch-FF Timing Advantage: Setup time can be negative: Transparency windowIs longer than the delay from input to the output.D injected afterthe clock.
53 CMOS Schmitt TriggerMoves switching thresholdof the first inverter
54 Schmitt Trigger Simulated VTC 2.52.52.02.0V1.5M11.5(V)(V)Xx1.0V1.0VM2Vk= 1k= 3k= 20.50.5k= 40.00.00.00.51.01.52.02.50.00.51.01.52.02.5V(V)V(V)ininVoltage-transfer characteristics with hysteresis.The effect of varying the ratio of thePMOS deviceM. The width isk* m.m4