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Instructor: Yuzhuang Hu Course Website The first lab is ready. The first assignment will be released.

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Presentation on theme: "Instructor: Yuzhuang Hu Course Website The first lab is ready. The first assignment will be released."— Presentation transcript:

1 Instructor: Yuzhuang Hu

2 Course Website The first lab is ready. The first assignment will be released soon.

3 Processes in VHDL The process is the primitive unit of behavioural description in VHDL. A clock example: entity clock is port (clock : out std_logic); end clock; architecture behav of clock is begin clock_process: process begin clock <= '1', '0' after 30 ns; wait for 30 ns; end process; end behav;

4 Processes and the Wait Statement Each process is associated with a sensitive list of signals. The body of the process will be executed only when events occur on at least one of the signals in the list. SUMPROC: process ( x, y, c_in) SUMPROC: process begin begin sum <= x xor y xor c_in after 2 ns; wait on x, y, c_in; end process SUMPROC; sum <= x xor y xor c_in after 2 ns; end process SUMPROC;

5 The Wait Statement The wait statement can be used to pause a process. It has four versions:  wait for 30 ns;  wait on x, y, c_in;  wait until x = ‘1’ and y = ‘1’;  wait;

6 Hierarchical Circuit Design Top-Down Approach: starting with the objective, finding some good way to break it down to simpler parts. Bottom-Up Approach: designing some low level circuits and building more complex components based on these circuits.

7 An Example: Adder/Subtractor The circuit looks complicated, but as we have already designed the full adder, we can treat the full adder as a black box. Architecture behav of Adder-Subtractor is signal s1, co1 : std_logic; Begin G1:xor_2 port map(INA=>sub, INB=>y0, Y=>s1); G1:FA port map(X=>x0, Y=>s1, C_in=>sub, SUM=>sum0, C_out=>co1); End behav;

8 Basic Types of Digital Circuits Combinational Circuits: outputs only depend on current inputs. An output is some function over the inputs. Sequential Circuits: outputs depend on both inputs and the current state of the circuit. Combinational circuit Inputs Storage Elements Outputs Next State Present State

9 Two Types of Sequential Circuits Asynchronous sequential circuits: the behaviour of such a circuit depends on the inputs at any instant of time and the order in continuous time in which the inputs change. Synchronous sequential circuits: outputs change at discrete times. Combinational Circuit Inputs Storage Elements Outputs Next State Present State Clock

10 Clocked Sequential Circuits Synchronization is achieved by a clock generator which produces a periodic train of clock pulse. Advantage: its simplicity and reliability. Disadvantage:  Consumption of power and dissemination of heats.  Every logic calculation in the circuit must finish within the clock cycle.

11 Storing Information A simple solution: connect the output to the input. Information can also be stored by combinational circuits with memory property.

12 SR Latch The same idea: connect outputs to inputs. R S Q Q RSQQ 1 0 0 0 0 1 0 0 1 1 1 0 0 1 0 0

13 SR Latch The same idea: connect outputs to inputs. S R Q Q RSQQ 0 1 1 1 1 0 1 1 0 0 1 0 0 1 1 1

14 SR Latch with Control Signals When the control input goes to 1, information from the S and R inputs is allowed to affect the outputs. S R Q Q C

15 D Latch Eliminate the undesirable undefined state in the SR latch: ensure S and R are never 1 at the same time. D Q Q C

16 Flip-Flops Latches are transparent: the state transition begins whenever the clock is on. Many latches may be connected together, in this case the final state depends on the length of the clock cycle. Flip-Flops eliminate this transparency.

17 SR Master-Slave Flip-Flop Two latches are combined such that  The inputs of the Flip-Flop control its state when a clock pulse is present.  The state of the Flip-Flop changes only when a clock pulse is not present. S C R S C R S C R

18 1s-Catching Behaviour of the SR master-slave Flip-FLop Assume Q is 0 and then the clock turns to 1. Consider a narrow 1-pulse of S after the clock becomes 1. As a result Q will be set to 1. Assume that the pulse is very narrow such that when S comes back to 0, the clock is still 1. Assume R is 0 all the time. Since Q is equal to 0 before the clock pulse and Q=1 after the clock pulse, the flip-flop is in the wrong state as S=R=0 just before the clock goes to 0.

19 Negative-Edge-Triggered D Flip- Flop 1s-Catching behaviour is eliminated as S and R can not both be 0 in a D Flip-Flop. D C D C S C R

20 Sequential Circuit Design Specification: write a specification of the circuit. Formulation: obtain a state diagram or a state table. Flip-Flop Input Equation Determination. Output Equation Determination. Optimization. Technology Mapping. Verification

21 An Example Sequential Circuit

22 State Equations A state equation specifies the next state as a function of the present state and the inputs. Define A(t) to be the value of A at time t. Then A(t+1) = A(t)x(t) + B(t)x(t), or can be simplified as A(t+1) = Ax + Bx.

23 State Tables The time sequence of inputs, outputs and states can be enumerated in a stable table. Present StateInputNext StateOutput ABXABY 000000 001010 010001 011110 100001 101100 110001 111100

24 State Diagram Mealy Model Circuit: The outputs depend on the inputs and the states. States are represented by circles. The input value during the present state precedes the slash, and the value following the slash gives the output value.

25 Moore Model Moore Model Circuit: The outputs depend only on the states.

26 A Sequence Recognizer Recognize 1101 from a longer sequence of bits. ABCD 0/01/0 0/0

27 Designing with D Flip-Flops Encode the states by Gray-Codes. Use a D flip-flop for each bit of the encoded states. Present StateNext StateOutput Z ABX=0X=1X=0X=1 00 0100 001100 101100 10000101

28 State-Machine Diagrams Drawbacks of the Mealy model and the Moore model: impractical for large design. All 2 n combinations of the n input variables must be specified in the diagram for state transitions. All 2 m combinations of the m output variables need to be specified. The Mealy model is very inefficient in specifying outputs.

29 State-Machine Diagrams contd. Use boolean expressions to simplify the diagram. S0S0 S1S1 S2S2 S3S3 Reset AB A (A+B)/Z A B/Y Z A B Y,Z A B/Y (A+B)/Y Inputs: A, B Outputs: Y, Z Defaults: Y=0,Z=0

30 Constraints on Input Conditions The transition conditions from a given state S i must be mutually exclusive. The transition conditions from a given state must cover all possible combinations of input values.

31 Constraints on Output Conditions For every output action in state S i or on its transitions having coincident output variables with differing values, the corresponding pair of output conditions must be mutually exclusive. For every output variable, the output conditions for state S i or its transitions must cover all possible combinations of input values that can occur.

32 Thanks!

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