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Computer Architecture I: Digital Design Dr. Robert D. Kent Logic Design Sequential Circuits Part I.

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1 Computer Architecture I: Digital Design Dr. Robert D. Kent Logic Design Sequential Circuits Part I

2 Review We have studied logic design in the contexts of Medium Scale Integration (MSI) of gate devices and programmable logic devices (PLD). We have studied the design of a number of specific, practical functional circuits with a view to re-using those circuits as components in MSI design. Adders Subtractors Comparator Decoders Multiplexers We note the differing design approaches, or emphases, effected by differential layering of abstraction. (The same design issue arises in the context of software engineering as well.) SSI: Boolean algebra / Simplification / Logic gates MSI: Interconnection networks / Iterative re-use / Components

3 Goals Previously, we studied Combinational circuits, or networks. –These are time independent because the inputs, once provided, immediately establish what the outputs will be.

4 Goals Previously, we studied Combinational circuits, or networks. –These are time independent because the inputs, once provided, immediately establish what the outputs will be. We now continue to consider Sequential Networks –These are time dependent in that the initial values of the circuit outputs are used to provide input to the same circuit.

5 Goals Previously, we studied Combinational circuits, or networks. –These are time independent because the inputs, once provided, immediately establish what the outputs will be. We now continue to consider Sequential Networks –These are time dependent in that the initial values of the circuit outputs are used to provide input to the same circuit. –This is called feedback.

6 Goals The properties of sequential networks yield the capability to design memory circuits –characterized by internal states and secondary states that describe the behaviour and values in a circuit before and after inputs are applied.

7 Goals The properties of sequential networks yield the capability to design memory circuits –characterized by internal states and secondary states that describe the behaviour and values in a circuit before and after inputs are applied. There are two kinds of sequential networks

8 Goals The properties of sequential networks yield the capability to design memory circuits –characterized by internal states and secondary states that describe the behaviour and values in a circuit before and after inputs are applied. There are two kinds of sequential networks –Synchronous - behaviour is governed by the inputs only during specific discrete time intervals

9 Goals The properties of sequential networks yield the capability to design memory circuits –characterized by internal states and secondary states that describe the behaviour and values in a circuit before and after inputs are applied. There are two kinds of sequential networks –Synchronous - behaviour is governed by the inputs only during specific discrete time intervals –Asynchronous - behaviour is governed by the inputs immediately as they are applied

10 Goals The basic logic element is called the Flip-Flop circuit.

11 Goals The basic logic element is called the Flip-Flop circuit. We will study first a primitive element - the basic bi-stable element.

12 Goals The basic logic element is called the Flip-Flop circuit. We will study first a primitive element - the basic bi-stable element. –... then study Latches.

13 Goals The basic logic element is called the Flip-Flop circuit. We will study first a primitive element - the basic bi-stable element. –... then study Latches. –... then proceed to Flip-Flops and Gated Latches/Flip-Flops.

14 Goals The basic logic element is called the Flip-Flop circuit. We will study first a primitive element - the basic bi-stable element. –... then study Latches. –... then proceed to Flip-Flops and Gated Latches/Flip-Flops. Finally, we will establish an MSI based model of a register and discuss how to construct load, read, shift and count capabilities into the register designs.

15 Basic Bi-stable Element The basic bi-stable element is a simple device characterized by –no inputs !!! –Two outputs.

16 Basic Bi-stable Element The basic bi-stable element is a simple device characterized by –no inputs !!! –Two outputs. This circuit has the representation: Q Q’ X X’ Y Y’

17 Basic Bi-stable Element The basic bi-stable element is a simple device characterized by –no inputs !!! –Two outputs. This circuit has the representation: Trace: Starting from the top gate 1. If X = 0 then Q = X’ = 1 Q Q’ X X’ Y Y’

18 Basic Bi-stable Element The basic bi-stable element is a simple device characterized by –no inputs !!! –Two outputs. This circuit has the representation: Trace: Starting from the top gate 1. If X = 0 then Q = X’ = 1 2. Thus, Y = X’ = Q = 1 implies Q’ = Y’ = 0 Q Q’ X X’ Y Y’

19 Basic Bi-stable Element The basic bi-stable element is a simple device characterized by –no inputs !!! –Two outputs. This circuit has the representation: Trace: Starting from the top gate 1. If X = 0 then Q = X’ = 1 2. Thus, Y = X’ = Q = 1 implies Q’ = Y’ = 0 This is self-consistent, since X = Y’ = Q’. Q Q’ X X’ Y Y’

20 Basic Bi-stable Element The basic bi-stable element is a simple device characterized by –no inputs !!! –Two outputs. This circuit has the representation: Trace: Starting from the top gate 1. If X = 0 then Q = X’ = 1 2. Thus, Y = X’ = Q = 1 implies Q’ = Y’ = 0 This is self-consistent, since X = Y’ = Q’. The same self-consistency applies when X = 1 (Y = 0). Therefore, we say the state is stable. Q Q’ X X’ Y Y’

21 Basic Bi-stable Element The basic bi-stable element is a simple device characterized by –no inputs !!! –Two outputs. This circuit has the representation: The term bi-stable implies that there are two possible states Q = 0, Q’ = 1 and Q = 1, Q’ = 0 Q Q’ X X’ Y Y’

22 Basic Bi-stable Element The basic bi-stable element is a simple device characterized by –no inputs !!! –Two outputs. This circuit has the representation: The term bi-stable implies that there are two possible states Q = 0, Q’ = 1 and Q = 1, Q’ = 0 –There is a third state that is technically possible, called the meta- stable state. This applies when the voltage signal values of X and Y (hence, Q and Q’) are precisely half way between their HI and LO values; however, these in-between states are typically short lived. Q Q’ X X’ Y Y’ Transition Voltage Q Q’ Smooth Signal Profile

23 Basic Bi-stable Element The basic bi-stable element is a simple device characterized by –no inputs !!! –Two outputs. This circuit has the representation: The term bi-stable implies that there are two possible states Q = 0, Q’ = 1 and Q = 1, Q’ = 0 –There is a third state that is technically possible, called the meta- stable state. This applies when the voltage signal values of X and Y (hence, Q and Q’) are precisely half way between their HI and LO values; however, these in-between states are typically short lived. Q Q’ X X’ Y Y’ Transition Voltage Q Q’ Noisy Signal Profile

24 Basic Bi-stable Element The basic bi-stable element is a simple device characterized by –no inputs !!! –Two outputs. This circuit has the representation: Although the bi-stable element is worth studying for its simple properties, it is relatively useless as a computer circuit because –its value cannot be changed from the “outside” - once power is applied its value is set (after a brief time period to achieve stability) and does not change henceforth. Q Q’ X X’ Y Y’

25 Latches

26 A Flip-Flop is a bistable device that permits both probing of its current state (value) and modification of the state.

27 Latches A Flip-Flop is a bistable device that permits both probing of its current state (value) and modification of the state. –Set the state - store a value 1 in the circuit; also called pre-setting the state.

28 Latches A Flip-Flop is a bistable device that permits both probing of its current state (value) and modification of the state. –Set the state - store a value 1 in the circuit; also called pre-setting the state. –Reset the state - store a value 0 in the circuit; also called clearing the state.

29 Latches A Flip-Flop is a bistable device that permits both probing of its current state (value) and modification of the state. –Set the state - store a value 1 in the circuit; also called pre-setting the state. –Reset the state - store a value 0 in the circuit; also called clearing the state. We will consider next a class of flip-flops called Latches.

30 Latches A Flip-Flop is a bistable device that permits both probing of its current state (value) and modification of the state. –Set the state - store a value 1 in the circuit; also called pre-setting the state. –Reset the state - store a value 0 in the circuit; also called clearing the state. We will consider next a class of flip-flops called Latches. –Characterized by the fact that the timing of the output changes is not controlled (except possibly by an Enable, or Clock, signal).

31 SR Latch

32 This circuit consists of two cross-coupled nor gates with –two inputs, S and R, referred to as set and reset inputs –two outputs, Q and Q’ RSRS Q Q’

33 SR Latch This circuit consists of two cross-coupled nor gates with –two inputs, S and R, referred to as set and reset inputs –two outputs, Q and Q’ Truth table: S R Q 0 Q 0 ’ Q 1 Q 1 ’ Q 2 Q 2 ’ RSRS Q Q’

34 SR Latch This circuit consists of two cross-coupled nor gates with –two inputs, S and R, referred to as set and reset inputs –two outputs, Q and Q’ Truth table: S R Q 0 Q 0 ’ Q 1 Q 1 ’ Q 2 Q 2 ’ RQ0’Q0SRQ0’Q0S Q Q’ Q 0 and Q 0 ’ are the output signal values when the S and R inputs are applied - they are also applied as inputs to the nor gates.

35 SR Latch This circuit consists of two cross-coupled nor gates with –two inputs, S and R, referred to as set and reset inputs –two outputs, Q and Q’ Truth table: S R Q 0 Q 0 ’ Q 1 Q 1 ’ Q 2 Q 2 ’ RSRS Q Q’ Once the nor gates have stabilized the outputs, Q 1 and Q 1 ’ are then fed back as inputs.

36 SR Latch This circuit consists of two cross-coupled nor gates with –two inputs, S and R, referred to as set and reset inputs –two outputs, Q and Q’ Truth table: S R Q 0 Q 0 ’ Q 1 Q 1 ’ Q 2 Q 2 ’ RSRS Q Q’ The nor gates must stabilize to a final output, Q 2 and Q 2 ’.

37 SR Latch This circuit consists of two cross-coupled nor gates with –two inputs, S and R, referred to as set and reset inputs –two outputs, Q and Q’ Truth table: S R Q 0 Q 0 ’ Q 1 Q 1 ’ Q 2 Q 2 ’ Q Q’

38 SR Latch This circuit consists of two cross-coupled nor gates with –two inputs, S and R, referred to as set and reset inputs –two outputs, Q and Q’ Truth table: S R Q 0 Q 0 ’ Q 1 Q 1 ’ Q 2 Q 2 ’ Q Q’

39 SR Latch This circuit consists of two cross-coupled nor gates with –two inputs, S and R, referred to as set and reset inputs –two outputs, Q and Q’ Truth table: S R Q 0 Q 0 ’ Q 1 Q 1 ’ Q 2 Q 2 ’ Q Q’ Stable!

40 SR Latch This circuit consists of two cross-coupled nor gates with –two inputs, S and R, referred to as set and reset inputs –two outputs, Q and Q’ Truth table: S R Q 0 Q 0 ’ Q 1 Q 1 ’ Q 2 Q 2 ’ Q Q’

41 SR Latch This circuit consists of two cross-coupled nor gates with –two inputs, S and R, referred to as set and reset inputs –two outputs, Q and Q’ Truth table: S R Q 0 Q 0 ’ Q 1 Q 1 ’ Q 2 Q 2 ’ Q Q’

42 SR Latch This circuit consists of two cross-coupled nor gates with –two inputs, S and R, referred to as set and reset inputs –two outputs, Q and Q’ Truth table: S R Q 0 Q 0 ’ Q 1 Q 1 ’ Q 2 Q 2 ’ Q Q’ Stable!

43 SR Latch This circuit consists of two cross-coupled nor gates with –two inputs, S and R, referred to as set and reset inputs –two outputs, Q and Q’ Truth table: S R Q 0 Q 0 ’ Q 1 Q 1 ’ Q 2 Q 2 ’ Q Q’ > 0 1 > 1 Stable!

44 SR Latch This circuit consists of two cross-coupled nor gates with –two inputs, S and R, referred to as set and reset inputs –two outputs, Q and Q’ Truth table: S R Q 0 Q 0 ’ Q 1 Q 1 ’ Q 2 Q 2 ’ Q Q’

45 SR Latch This circuit consists of two cross-coupled nor gates with –two inputs, S and R, referred to as set and reset inputs –two outputs, Q and Q’ Truth table: S R Q 0 Q 0 ’ Q 1 Q 1 ’ Q 2 Q 2 ’ Q Q’ 0 > 0 1 > 0 1 > 0 0 > 0

46 SR Latch This circuit consists of two cross-coupled nor gates with –two inputs, S and R, referred to as set and reset inputs –two outputs, Q and Q’ Truth table: S R Q 0 Q 0 ’ Q 1 Q 1 ’ Q 2 Q 2 ’ * Stable! 1010 Q Q’ 0 > 0 1 > 0 1 > 0 > 0 0 > 0 > 1

47 SR Latch This circuit consists of two cross-coupled nor gates with –two inputs, S and R, referred to as set and reset inputs –two outputs, Q and Q’ Truth table: S R Q 0 Q 0 ’ Q 1 Q 1 ’ Q 2 Q 2 ’ * Q Q’

48 SR Latch This circuit consists of two cross-coupled nor gates with –two inputs, S and R, referred to as set and reset inputs –two outputs, Q and Q’ Truth table: S R Q 0 Q 0 ’ Q 1 Q 1 ’ Q 2 Q 2 ’ * Q Q’ 1 > 0 0 > 0 0 > 0 1 > 0

49 SR Latch This circuit consists of two cross-coupled nor gates with –two inputs, S and R, referred to as set and reset inputs –two outputs, Q and Q’ Truth table: S R Q 0 Q 0 ’ Q 1 Q 1 ’ Q 2 Q 2 ’ * * 0101 Q Q’ 1 > 0 0 > 0 0 > 0 > 1 1 > 0 > 0 Stable!

50 SR Latch This circuit consists of two cross-coupled nor gates with –two inputs, S and R, referred to as set and reset inputs –two outputs, Q and Q’ Truth table: S R Q 0 Q 0 ’ Q 1 Q 1 ’ Q 2 Q 2 ’ * * Q Q’ 0 > 0 1 > 1 1 > 1 0 > 0 Stable!

51 SR Latch This circuit consists of two cross-coupled nor gates with –two inputs, S and R, referred to as set and reset inputs –two outputs, Q and Q’ Truth table: S R Q 0 Q 0 ’ Q 1 Q 1 ’ Q 2 Q 2 ’ * * x x Q Q’ x > 0 Stable! But not complementary! ( Q = Q’ )

52 SR Latch This circuit consists of two cross-coupled nor gates with –two inputs, S and R, referred to as set and reset inputs –two outputs, Q and Q’ Truth table: (Adapted) S R Q 0 Q 0 ’ Q 2 Q 2 ’ Q + Q + ’ Q Q’ Q Q’ * * x x 0 0 Forbidden RSRS Q + Q + ’

53 SR Latch This circuit consists of two cross-coupled nor gates with –two inputs, S and R, referred to as set and reset inputs –two outputs, Q and Q’ Truth table: (Adapted - Simplified) S R Q Q (0) Forbidden RSRS Q + Q + ’

54 SR Latch This circuit consists of two cross-coupled nor gates with –two inputs, S and R, referred to as set and reset inputs –two outputs, Q and Q’ Truth table: (Adapted - Simplified) S R Q Q (0) Forbidden RSRS Q + Q + ’ S Q R Q’ S Q R Q Two commonly used MSI symbols.

55 S’R’ Latch

56 This circuit consists of two cross-coupled nand gates with –two complemented inputs, S’ and R’, referred to as set and reset inputs –two outputs, Q + and Q + ’ S’ R’ Q + Q + ’

57 S’R’ Latch This circuit consists of two cross-coupled nand gates with –two complemented inputs, S’ and R’, referred to as set and reset inputs –two outputs, Q + and Q + ’ Truth table: S’ R’ Q (1) Forbidden 0 Q + = 1 Q + ’ = 1

58 S’R’ Latch This circuit consists of two cross-coupled nand gates with –two complemented inputs, S’ and R’, referred to as set and reset inputs –two outputs, Q + and Q + ’ Truth table: S’ R’ Q (1) Forbidden S’ = 0 R’ = 1 Q + = 1 Q + ’ = 0

59 S’R’ Latch This circuit consists of two cross-coupled nand gates with –two complemented inputs, S’ and R’, referred to as set and reset inputs –two outputs, Q + and Q + ’ Truth table: S’ R’ Q (1) Forbidden S’ = 1 R’ = 0 Q + = 0 Q + ’ = 1

60 S’R’ Latch This circuit consists of two cross-coupled nand gates with –two complemented inputs, S’ and R’, referred to as set and reset inputs –two outputs, Q + and Q + ’ Truth table: S’ R’ Q (1) Forbidden Q S’ = 1 R’ = 1 Q + = Q Q + ’ = Q’

61 S’R’ Latch This circuit consists of two cross-coupled nand gates with –two complemented inputs, S’ and R’, referred to as set and reset inputs –two outputs, Q + and Q + ’ Truth table: S’ R’ Q (1**) Q S’ R’ Q + Q + ’ Two commonly used MSI symbols. S Q R Q’ S Q R Q

62 D Flip-Flop

63 The D flip-flop overcomes the problem of the SR (S’R’) latch having forbidden states. It features a single input, D, and a control input, Clk, provided by the system clock, and produces outputs Q and Q’. (Enable) Clk D Q Q’

64 D Flip-Flop The D flip-flop overcomes the problem of the SR (S’R’) latch having forbidden states. It features a single input, D, and a control input, Clk, provided by the system clock, and produces outputs Q and Q’. –Note the SR latch sub-circuit element (Enable) Clk D Q Q’

65 D Flip-Flop The D flip-flop overcomes the problem of the SR (S’R’) latch having forbidden states. It features a single input, D, and a control input, Clk, provided by the system clock, and produces outputs Q and Q’. –Note the SR latch sub-circuit element –The control input, Clk, controls a sub-circuit called a “gate”. (Enable) Clk D Q Q’

66 D Flip-Flop The D flip-flop overcomes the problem of the SR (S’R’) latch having forbidden states. It features a single input, D, and a control input, Clk, provided by the system clock, and produces outputs Q and Q’. –Note the SR latch sub-circuit element –The control input, Clk, controls a sub-circuit called a “gate”. Since D is the only input, the forbidden values, S = R = 1, never occur. (Enable) Clk D Q Q’

67 D Flip-Flop The D flip-flop overcomes the problem of the SR (S’R’) latch having forbidden states. It features a single input, D, and a control input, Clk, provided by the system clock, and produces outputs Q and Q’. –Note the SR latch sub-circuit element –The control input, Clk, controls a sub-circuit called a “gate”. Since D is the only input, the forbidden values, S = R = 1, never occur. (Enable) Clk D Q Q’ 0 0 When Clk = 0, it follows that: S = R = 0 This implies no change of state: Q + = Q

68 D Flip-Flop The D flip-flop overcomes the problem of the SR (S’R’) latch having forbidden states. It features a single input, D, and a control input, Clk, provided by the system clock, and produces outputs Q and Q’. –Note the SR latch sub-circuit element –The control input, Clk, controls a sub-circuit called a “gate”. Since D is the only input, the forbidden values, S = R = 1, never occur. (Enable) Clk D Q Q’ D’ D 1 When Clk = 1, it follows that: S = D and R = D’ Thus, the behaviour is: D = S = 1 Q + = 1 D = 0 (R = 1) Q + = 0

69 JK Flip-Flop

70 The basic JK flip-flop provides a solution to the problem of the SR latch with S=R=1 that produces forbidden output states.

71 JK Flip-Flop The basic JK flip-flop provides a solution to the problem of the SR latch with S=R=1 that produces forbidden output states. The JK flip-flop can be constructed from the gated SR latch by coupling additional feedback from the (Q, Q’) outputs into the J and K inputs. J Clk K Q Q’ S Q C Q R

72 JK Flip-Flop The basic JK flip-flop provides a solution to the problem of the SR latch with S=R=1 that produces forbidden output states. The JK flip-flop can be constructed from the gated SR latch by coupling additional feedback from the (Q, Q’) outputs into the J and K inputs. With the clock disabled (C = 0) the SR latch retains the state (Q, Q’). J Clk K Q Q’ S Q C Q R 0

73 JK Flip-Flop The basic JK flip-flop provides a solution to the problem of the SR latch with S=R=1 that produces forbidden output states. The JK flip-flop can be constructed from the gated SR latch by coupling additional feedback from the (Q, Q’) outputs into the J and K inputs. With the clock enabled (C = 1) the SR latch produces outputs that depend on the J and K inputs. J Clk K Q Q’ S Q C Q R 1

74 JK Flip-Flop TRACE The JK flip-flop can be constructed from the gated SR latch by coupling additional feedback from the (Q, Q’) outputs into the J and K inputs. We denote the final output as Q +. J KJ K Q Q’ This leads to the algebraic expression for the final output, labeled Q +, in terms of J, K and initial input Q: Q + = JQ’ + K’Q META-STABLE ! J K Q in Q out Actions: J=K=0 Do nothing J=1, K=0 Set Q=1 J=0, K=1 Reset Q=0 J=K=1 Complement Q = Q’

75 JK Flip-Flops – edge triggering The previous implementation of a JK flip-flop is considered unstable under certain circumstances. Utilizing an edge-triggered master-slave latch is used to produce a stable circuit. –Below is given a more typical JK using a master-slave approach –WARNING: Tracing the logic may prove confusing as the actual circuits employ both leading-edge and trailing-edge gate elements in order to avoid forbidden states. Q

76 JK, D and T Flip-Flops JK flip-flops can be used to produce –D flip-flops Connect K to J using an inverter so they have different values –T flip-flops Sometimes called a complementer Connect J and K so they have the same values –If J = K = 0, nothing happens (Q stays the same) –If J = K = 1, the complement of Q is outputted This illustrates, once again, the principle that common components can be used to achieve design goals in different ways.

77 Timing Considerations

78 Real (physical) circuit elements take a finite time to respond to the stimulus of changing state (voltage). The behaviour of a logic device is characterized by the following times:

79 Timing Considerations Real (physical) circuit elements take a finite time to respond to the stimulus of changing state (voltage). The behaviour of a logic device is characterized by the following times: –Propagation Delay The time it takes to produce a change in an output signal based on the input signals. S R Q Q’ T p,HL T p,LH

80 Timing Considerations Real (physical) circuit elements take a finite time to respond to the stimulus of changing state (voltage). The behaviour of a logic device is characterized by the following times: –Propagation Delay The time it takes to produce a change in an output signal based on the input signals. S R Q Q’ As the value of S begins to change, it is only when it has reached a certain voltage level that the value of Q (Q’) begins to change. S must be maintained at a certain level for a minimum time period before Q can stabilize. T p,HL T p,LH

81 Timing Considerations Real (physical) circuit elements take a finite time to respond to the stimulus of changing state (voltage). The behaviour of a logic device is characterized by the following times: –Propagation Delay –Minimum Pulse Width The minimum amount of time an input signal must be applied in order to produce a change in the output. SRQSRQ

82 Timing Considerations Real (physical) circuit elements take a finite time to respond to the stimulus of changing state (voltage). The behaviour of a logic device is characterized by the following times: –Propagation Delay –Minimum Pulse Width –Setup Time - the minimum time the input signals must be held fixed before the latching action begins

83 Timing Considerations Real (physical) circuit elements take a finite time to respond to the stimulus of changing state (voltage). The behaviour of a logic device is characterized by the following times: –Propagation Delay –Minimum Pulse Width –Setup Time - the minimum time the input signals must be held fixed before the latching action begins –Hold Time - the minimum time the input signals must be held fixed until the latching action is completed

84 State Tables and Diagrams

85 Complex circuits are difficult to represent simply in a compact notation. –State tables are a form of truth tables where current values of flip-flop outputs are used as inputs, along with other specified inputs, to determine outputs after a clock pulse.

86 State Tables and Diagrams Complex circuits are difficult to represent simply in a compact notation. –State diagrams are graphical representations of all possible transitions that are described by a state table. Example: JK flip-flop Present State InputsNext state Q(t)JKQ(t+1)

87 State Tables and Diagrams Complex circuits are difficult to represent simply in a compact notation. –State diagrams are graphical representations of all possible transitions that are described by a state table. Example: JK flip-flop Present State InputsNext state Q(t)JKQ(t+1) Draw possible Q output states in circles (or ellipses)

88 State Tables and Diagrams Complex circuits are difficult to represent simply in a compact notation. –State diagrams are graphical representations of all possible transitions that are described by a state table. Example: JK flip-flop Present State InputsNext state Q(t)JKQ(t+1) ,01

89 State Tables and Diagrams Complex circuits are difficult to represent simply in a compact notation. –State diagrams are graphical representations of all possible transitions that are described by a state table. Example: JK flip-flop Present State InputsNext state Q(t)JKQ(t+1) ,01 10,11

90 State Tables and Diagrams Complex circuits are difficult to represent simply in a compact notation. –State diagrams are graphical representations of all possible transitions that are described by a state table. Example: JK flip-flop Present State InputsNext state Q(t)JKQ(t+1) ,01 00,10 10,11 01,11

91 State Tables and Diagrams Complex circuits are difficult to represent simply in a compact notation. –State diagrams are graphical representations of all possible transitions that are described by a state table. Example: JK flip-flop Present State InputsNext state Q(t)JKQ(t+1) ,01 00,10 10,11 01,11 Draw transitions between output states. Allow for no change of value, as well as changes in value. Label each transition by the (list) of all JK inputs that effect the transition. If the inputs are themselves changed in transition, list the initial and final input values separated by a slash ‘/’.

92 Characteristic Equations

93 Before proceeding, we stop briefly to recapitulate the various basic flip-flop circuits derived so far. Each circuit has an associated set of expressions that describe the outputs in terms of the inputs and the internal state at the time the circuit is enabled. These expressions are called the characteristic equations.

94 Characteristic Equations S Q C R Q’ SR flip-flop Q + = S + R’Q : (SR) = 0 Q+ refers to the output value after the next clock interval, or Q(t+1).

95 Characteristic Equations S Q C R Q’ SR flip-flopD flip-flop Q + = S + R’Q : (SR) = 0Q + = D D Q C Q’

96 Characteristic Equations J Q C K Q’ S Q C R Q’ SR flip-flopD flip-flop JK flip-flop Q + = S + R’Q : (SR) = 0Q + = D Q + = JQ’ + K’Q D Q C Q’

97 Characteristic Equations J Q C K Q’ S Q C R Q’ SR flip-flopD flip-flop JK flip-flop T flip-flop Q + = S + R’Q : (SR) = 0Q + = D Q + = JQ’ + K’Q Q + = TQ’ + T’Q = T xor Q D Q C Q’ T Q C Q’

98 Gated Latches

99 The concept of a gate, or a controlling element, is important in computer circuits. During the execution of a program only specific circuit elements should be active at a given time. These are often controlled using a strobe signal that provides a regular sequence of alternating voltage-HI (1) and voltage-LO (0) signals. Because of the regular nature of the signal sequence the strobe is called a “clock”. Thus, gate control is often achieved using a clock. Another type of control signal is called an “enable” signal.

100 Gated SR Latch

101 The SR latch is modified to a gated SR latch by applying a clock signal to the latch input. S (Enable) Clk R Q Q’

102 Gated SR Latch The SR latch is modified to a gated SR latch by applying a clock signal to the latch input. This gives rise to the behaviour: Clk = 0 S (Enable) Clk R Q Q’ 0

103 Gated SR Latch The SR latch is modified to a gated SR latch by applying a clock signal to the latch input. This gives rise to the behaviour: Clk = 0 S (Enable) Clk R Q Q’ Q’ Q

104 Gated SR Latch The SR latch is modified to a gated SR latch by applying a clock signal to the latch input. This gives rise to the behaviour: Clk = 0 S (Enable) Clk R Q Q’ Q’ Q Q Q’

105 Gated SR Latch The SR latch is modified to a gated SR latch by applying a clock signal to the latch input. This gives rise to the behaviour: Clk = 0 The outputs (Q, Q’) remain unchanged when the circuit is disabled. The (Q,Q’) are stored in a stable manner. S (Enable) Clk R Q Q’ Q’ Q Q Q’

106 Gated SR Latch The SR latch is modified to a gated SR latch by applying a clock signal to the latch input. This gives rise to the behaviour: Clk = 1 S (Enable) Clk R Q Q’ 1

107 Gated SR Latch The SR latch is modified to a gated SR latch by applying a clock signal to the latch input. This gives rise to the behaviour: Clk = 1 The first stage nand gates are activated by the Clk signal to produce the outputs (S’, R’). S (Enable) Clk R Q Q’ S’ R’ 1

108 Gated SR Latch The SR latch is modified to a gated SR latch by applying a clock signal to the latch input. This gives rise to the behaviour: Clk = 1 The first stage nand gates are activated by the Clk signal to produce the outputs (S’, R’). The remaining sub-circuit is just an S’R’ latch whose properties were discussed previously. S (Enable) Clk R Q Q’ S’ R’ 1

109 Gated SR Latch The SR latch is modified to a gated SR latch by applying a clock signal to the latch input. This gives rise to the behaviour: Clk = 1 The first stage nand gates are activated by the Clk signal to produce the outputs (S’, R’). The remaining sub-circuit is just an S’R’ latch whose properties were discussed previously. S (Enable) Clk R Q Q’ S’ R’ 1 The effect of the Clk input is to control the latch circuit. Changes to (Q,Q’) may only occur when Clk=1 enables the circuit.

110 Gated D Latch

111 We previously considered this circuit. See earlier notes. (Enable) Clk D Q Q’

112 Gated D Latch We previously considered this circuit. See earlier notes. The MSI representation may be given in two forms: (Enable) Clk D Q Q’ D Q C Q’ D Q C Q (A) (B)

113 Master-Slave Flip-Flops

114 We have just considered the category of flip-flops called latches. –Changes on the information input lines produce immediate responses on the output lines. –This is called transparency. Now we consider the category of Master-Slave (pulse-triggered) flip-flop circuits. –These circuits feature a control signal that enables one stage of a circuit while disabling a second stage, then the second stage is enabled while the first stage is disabled. –This is called cascading of circuits.

115 Master-Slave SR Flip-Flop

116 The SR flip-flop is adapted to the Master-Slave flip-flop by cascading two SR circuits with sequential enabling of each circuit by a Clk pulse.

117 Master-Slave SR Flip-Flop The SR flip-flop is adapted to the Master-Slave flip-flop by cascading two SR circuits with sequential enabling of each circuit by a Clk pulse. S Q C R Q QMQM’QMQM’ SCRSCR QSQS’QSQS’ Q Q’

118 Master-Slave SR Flip-Flop The SR flip-flop is adapted to the Master-Slave flip-flop by cascading two SR circuits with sequential enabling of each circuit by a Clk pulse. –When the clock is set, C = 1, the first stage gated SR latch is enabled, but the second stage is disabled. S Q C R Q QMQM’QMQM’ SCRSCR QSQS’QSQS’ Q Q’ 10

119 Master-Slave SR Flip-Flop The SR flip-flop is adapted to the Master-Slave flip-flop by cascading two SR circuits with sequential enabling of each circuit by a Clk pulse. –When the clock is set, C = 1, the first stage gated SR latch is enabled, but the second stage is disabled. –When the clock signal returns to C = 0, the first stage is disabled and the second stage is enabled. S Q C R Q QMQM’QMQM’ SCRSCR QSQS’QSQS’ Q Q’ 10

120 Registers

121 A register is a collection of flip-flops taken as a single entity. Since flip-flops are memory units for single bits, then registers are the equivalent, multi-bit storage units. –Since registers are comprised of a finite number, N, of flip-flops, the total number of 0 and 1 combinations is 2 N. –Each of these combinations is known as the content or state of the register. In addition to storage alone, registers may also have other capabilities associated with them. –Clear, Load, Shift, Count

122 Registers A simple storage register based on the Master-Slave D flip-flop is constructed by chaining n of them as shown. The entire memory unit is controlled by the Clock (C) pulse. D Q C Q’ Q0Q0’Q1Q1’Q0Q0’Q1Q1’ D0D1CD0D1C D 0 Q 0 Q 0 ’ D 1 Q 1 Q 1 ’... D n-1 Q n-1 Q’ n-1 C

123 Registers In a similar fashion, the Master-Slave T flip-flop is constructed by chaining n of them as shown, controlled by the clock (C) pulse. T Q C Q’ Q0Q0’Q1Q1’Q0Q0’Q1Q1’ T0T1CT0T1C T 0 Q 0 Q 0 ’ T 1 Q 1 Q 1 ’... T n-1 Q n-1 Q’ n-1 C

124 Registers Thus, a register is a special multi-bit storage unit that is used to store data in a collective representation (eg. signed binary, BCD, and so on). D 0 Q 0 Q 0 ’ D 1 Q 1 Q 1 ’... D n-1 Q n-1 Q’ n-1 Enable I 0 I 1 I n-1 Clock Enable N-bit Register Q 0 Q 1 Q n-1 Stored Values (Potential output) Input Data

125 Registers We will discuss registers in more detail due to their importance in CPU design and in other places in a computer CPU registers used in the textbook (Mano): –PC :: Program counter –IR :: Instruction register –AR :: Address register –DR :: Data register –AC :: Accumulator –INR :: Input buffer register –OUTR :: Output buffer register –SCR :: Sequence counter register (or just SC)

126 Summary We considered details and MSI views of: –Latches: SR, S’R’, D –Gated Latches: SR, D –Master-Slave: SR, JK, D, T We also discussed the issue of timing and response as important behaviours that characterize and typify logic devices. –Including propagation delay, minimum pulse width, set-up and hold times. We concluded by considering registers as conceptual extensions of the basic flip-flops.


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