1. Wide Range SET Pulse Measurement Robert L. Shuler, Jr. – NASA/JSC – robert.l.shuler@nasa.govrobert.l.shuler@nasa.gov Li Chen – University of Saskatchewan – li.chen@usask.cali.chen@usask.ca Single Event Effects Symposium April 2012 La Jolla, CA

2. Brief history of SET measurement Variable Temporal Latch ◦ Eaton et. al. 2004 [1] ◦ Flip flops tuned to detect pulses in excess of a threshold ◦ Hours of testing at different thresholds to fully characterize Capture Latch Delay Line ◦ Narasimham et. al. 2005 [2] ◦ Footprint of pulse captured at end of latch chain ◦ Chain must accommodate longest pulse ◦ Absorption issues, latch chain attenuates short pulses Capture latch improvements ◦ Shuler & Narasimham et. al. 2007 [3] ◦ Ion collector of merged inverter chains to feed capture chain ◦ Capture pulses at front of latch chain via trailing edge trigger, to reduce absorption

3. Issues in SET measurement Importance of very short pulses in error rates ◦ Indirect inference by Balasubramanian et. al. 2008 [5] ◦ From high total dose suppression short pulses ◦ Short pulses account for large % of SETs that become SEUs Direct measurement of charge sharing SETs ◦ Triple-interleaved inverter string suggested by Bhuva and Narasimham, implemented by Shuler 2009 ◦ Bench testing showed pulse distortion due to unexpected intra- string coupling, roughly confirmed by simulation Discrepancy between reported SETs & SEUs ◦ Carmichael et. al. (Xilinx) 2010 [4] ◦ Differences between error rates of delay protected flip flops and SET lengths & rates reported by tuned flip flops

4. Goals / Approach Use fast dynamic logic to measure short pulses Use a weighted binning to accurately resolve short pulses while measuring longer ones Develop a way to collect & measure SETs from Combinational logic Passgate routing networks Fix pulse distortion in charge sharing experiment Alternate the adjacency pattern for interleaved inverter strings

5. Dynamic Logic Node is preset by clock and discharged by logic signals ◦ Eliminates most PFET loads ◦ Trailing edge of pulse will not propagate Easy to implement weighted binning by varying propagation delay Node charge is vulnerable ◦ Important to investigate error rates in measurement circuit Domino Logic AND (left) and OR (right) gates

6. Comparison of methods (based on simulation)

7. Compact wide range SET capture circuit SET propagates through DL-OR gates, which are copied to DL-AND gates ◦ Extra gate loads provide process independent delay weighting for later stages Trailing edge trigger freezes SET pattern in DL-AND gates ◦ Pattern copied to DICE latches for serial readout ◦ Two stage copy (DL-OR  DL-AND  DICE) avoids static logic gate loads on early capture stages

8. Stage delays (bins) for TSMC 0.35  First stage is a little longer due to trailing edge trigger logic load (in practice, no SET triggered less than 2 stages) 10 stages do the work of a 20 stage capture latch chain 1.3 ns (guard delay, used later) is 6 or 7 stages (too close to call)

9. 64 to 1 SET merge collector Logic to be tested Bench test signal Provision to alternate logic state SET detection buffers Fast NAND merge 8 to 1 fast NAND merge

10. Test cases (64 of each) 1. Adder with 4 to 1 input mux 2. NFET routing matrix (4x4 configured as 16 to 1) 3. No logic & no merge tree (allows evaluation of error rate in dynamic logic capture circuit)

11. Charge-sharing ion collector 6 strings of inverters, each 17 x 4-merged to minimize length, alternating adjacency placement Note: this feeds 6 independent SET capture circuits Test circuit injects pulses of 4, 8, 12 inverter delays, or unlimited, for bench test of all functions

12. Testing Laser at University of Saskatchewan Heavy ions at TAMU

13. 0.35  laser testing Pulse propagation quality ◦ Problem with interleaved multi-string ion collector is improved  3 stage typical capture with laser focused at last stage before ion collector  3 +/-1 with laser focused at first stage   pulse spreading/contraction no larger than 1 capture stage ◦ A minimum detectable pulse can propagate through the ion collector  2 stages was the minimum pulse width measured in any test ◦ 64 to 1 merge quality  8 capture-stage hits in final NAND (loading?)  2-3 stage SETs typical of other NAND hits  No hits recorded on inverters at laser energy SET variation with Vdd ◦ 3.3v is process nominal Vdd ◦ SETs decrease ~20% at 1.8v  Correlation with SEU investigated in heavy ion test 6-string ion collector, pulses injected half way back Used scanning mode for this test. (hot spots too difficult to find) 3 +/-1 typical for narrow beam width. Longer SETs are with wider beam setting.

14. Heavy ion testing – logic SETs total "effective" fluence all runs = 1e7 ions/cm^2 SETs in capture circuit (nocl) are few and short, probably in trigger logic Excess short SETs far above distribution curve for normal SETs Routing matrix (nfet) somewhat worse than combinational logic, as expected ◦ Except in the case of along-the-row incident angle, which for combinational logic is very bad Results from along-row incidence confirm multi-node charge collection [6] Unfortunately, no test circuit included to measure SETs from 64 to 1 merge LET Logic type Number of SETs Length of SETs (capture stages) Gold 0 ° Gold 60 ° cross-row Gold 60 ° along cell row

15. Heavy ion testing – charge sharing cross row along row Typical pulse lengths ◦ Primary hit consistent with data from combinational logic tests ◦ Shared hits typically 2 or 3 capture stages (.3-.5ns, close to minimum recorded pulses) Summary SET counts ◦ No charge sharing measured below LET of 88 (likely exists as shorter pulses than.3ns, but no opportunity for combination to form a significant pulse as they might in ordinary logic) ◦ 3-string charge sharing detected at LET of 176, in greater amounts for along- row strikes.  Each stage of 6 adjacent inverters is side by side in a placement cell, affording max opportunity for charge sharing with along-row strikes ◦ This test is largely proof-of-concept, as not a serious problem for 0.35 

16. SEU test circuits for correlation with SET results For each flip flop type ◦ 48 pair with XOR ◦ Combinational logic  Same as SET tests  Adder with 4-1 mux ◦ Clocked at 50 MHz 3 flip flop types: ◦ DICE ◦ DICE with 1.3ns delay on 2 nd input ◦ DICE with separation of critical nodes + delay DICE latches D Flip Flop:

17. DICE failures begin at LET=88 ◦ Charge sharing and long SETs both show up at LET=88 Delay protection is effective ◦ Critical node separation offers no discernable advantage at 0.35m ◦ Combinational logic SETs are far dominating multi-node SETs? ◦ At LET=176, do very long SETs overwhelm the delay protection?  Very possible from 176 along-row SET data with SETs up to 2ns  NOT obvious from 88 vs. 176 cross-row data (which has fewer and shorter SETs than LET=88 data)  Possibly higher rate at 176 is due to long SET in the delay circuit itself … would be useful to measure SET from the delay! Reversal of strategy at low Vdd ◦ Lower charge collected, circuit slows more than SETs lengthen ◦ Ordinary DICE is much better ◦ Errors presumably from long SET in delay circuit itself (again useful to measure delay circuit SET) SEU heavy ion test data total "effective" fluence all runs = 1e7 ions/cm^2; plotting events vs. LET Vdd=3.3v 50 MHz Vdd=3.3v 50 MHz Vdd=1.8v 6.25 MHz

18. Conclusions & future plans Dynamic logic SET capture provides better measurement ◦ Errors in dynamic gates are lower than expected, basically negligible ◦ Performance is verified and calibrated with bench tests ◦ Circuit is both faster and more compact, allowing more measurement Combination logic SET measurement confirms theories ◦ Routing is a significant source of SET ◦ Multi-node SET combination is confirmed ◦ Results can be correlated to flip flop SEUs Evaluation & improvement of merge network needed ◦ Need separate characterization of SET from merge ◦ Use dynamic logic for merge and begin capture in merge stages Charge sharing measurement architecture confirmed ◦ Needs to be applied in deep submicron Work continuing at 90nm, possibly 65nm, through U. Sas. ◦ Repeat critical node vs. delay-only protection analysis, should be different ◦ Much lower cost foundry access in Canada, but also long cycle times ◦ May not have area / pinouts to repeat charge sharing direct measurement Collaborators to share test runs would be greatly appreciated!

19. References [1] P. Eaton, J. Benedetto, D. Mavis, K. Avery, M. Sibley, M. Gadlage, and T. Turflinger, Single Event Transient Pulsewidth Measurements Using a Variable Temporal Latch Technique, IEEE TNS, VOL. 51, NO. 6, DEC 2004 [2] B. Narasimham, V. Ramachandran, B. L. Bhuva, R. D. Schrimpf, A. F. Witulski, W. T. Holman, L. W. Massengill, J. D. Black, W. H. Robinson and D. McMorrow, On-chip Characterization of Single Event Transient Pulse Widths, IEEE TNS, VOL. 52, NO. 6, DEC 2005 [3] R. L. Shuler, A. Balasubramanian, B. Narasimham, B. Bhuva, P. M. O’Neill, C. Kouba, The Effectiveness of TAG or Guard-Gates in SET Suppression Using Delay and Dual-Rail Configurations at 0.35 um, IEEE TNS, VOL. 54, NO. 6, DEC 2007 [4] C. Carmichael, G. Swift, C. W. Tseng, E. Miller, Characterization & Filtration of Single Event Transient Effects in 65nm CMOS Technology, Single Event Effects Symposium, La Jolla, CA 2010 [5] A. Balasubramanian, B. Narasimham, B. L. Bhuva, L. W. Massengill, P. H. Eaton, M. Sibley, D. Mavis, Implications of Total Dose on Single-Event Transient (SET) Pulse Width Measurement Techniques, IEEE TNS, VOL. 55, NO. 6, DEC 2008 [6] B. Narasimham, O. Amusan, B. Bhuva, R. Schrimpf, W. Holman, Extended SET Pulses in Sequential Circuits Leading to Increased SE Vulnerability, IEEE TNS, Vol. 55, No. 6, DEC 2008