# Switch Debouncing. Switches connected to sources of constant logic 0 and 1 are often used in digital systems to supply “user inputs”. In high speed digital.

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Switch Debouncing

Switches connected to sources of constant logic 0 and 1 are often used in digital systems to supply “user inputs”. In high speed digital logic applications we must consider another aspect of switch operation, the time dimension. A simple make or brake operation, which occurs instantly as far as we slow-moving humans are concerned, actually has several phases that are distinguishable by high-speed digital logic.

Switch Debouncing Figure (a) shows how a single-pole-single-through (SPST) switch might be used to generate a single logic input. A pull-up resistor provides a logic-1 when the switch is opened, and the switch contact is tied to ground to provide a logic-0 when the switch is pushed. As shown in (b), it takes a while after a push for the wiper to hit the bottom contact. Once it hits, it does not stay there for long; it bounces a few times before finally settling. The result is that several transitions are seen on the SW_L and DSW logic signals for each single switch push. This behaviour is called contact bounce. Typical switches bounce for 10-20 ms, a very long time compared to the switching speeds of logic gates.

Switch Debouncing

This contact bounce is a problem if a switch is being used to count or signal the clock events for our lab exercise. Then we must provide a circuit to debounce the switch - to provide just one signal change or pulse for each switch push.

Simplest Switch Debouncer The simplest sequential circuit can be used to make the simplest switch debouncer as shown in figure (a). This circuit uses a single-pole-double-through (SPDT) switch. Feedback in the bistable holds SW at V OL, a valid logic 0. Feedback in the bistable maintains the logic 0 on SW_L even if the wiper bounces off the bottom contact. It does not bounce far enough to touch the top contact again.

Simplest Switch Debouncer

Switch Debouncing using S’R’ latch In situations where momentarily shorting gate outputs must be avoided, a similar circuit can be designed using S’R’ latch and pull-up resistors as shown in figure.

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