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Practice Problems 2 Latch and Flip Flop ©Paul Godin Created September 2007 Last edit Aug 2013

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Introduction The following slides contain practice problems Solutions are provided at the end of this presentation 2

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Hints Mark the clock edges. In some configurations where the output of a flip-flop becomes the input to another, look at the input states immediately prior to the edge. You must remember the truth tables for the flip- flops. 3

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Problem #1 4

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Problem #2 5

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Problem #3 6

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Problem #4 7

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Problem #5 8

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Problem #6 9

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SOLUTIONS 10

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Introduction The following slides contain timing diagram solutions and a brief discussion. 11

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Discussion #1 This problem involves a more complex approach. We notice that the second flip-flop gets its edge from the Q’ of the first. We need to draw the Q’ output timing diagram to help us determine the edges. We also noticed that the J and K inputs to FF#2 are tied together, and follow the J input. Therefore, there can only be 2 states to FF#2: 11 and 00 (Toggle and Hold). If J input=1, FF#2 toggles. In the solution, I’ve indicated the JK states next to each edge. Problem #1 12

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Problem #1 13

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Discussion #2 This problem is a little simpler than the previous exercise. The similarity is that FF#1 is producing the edge for FF#2 (asynchronous configuration), and so we must solve for FF#1 before FF#2. Problem #2 14

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Problem #2 15

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Discussion #3 The method of solving this problem is to visualize the input state just prior to the edge. Again, this is an asynchronous configuration where the 2nd FF gets its trigger from the first. This configuration creates a recognizable output pattern. Problem #3 16

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Problem #3 17

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Discussion #4 This is perhaps the simplest of these practice problems. This configuration, where each FF gets the same clock edge, is called Synchronous. The FFs are independent and are treated individually. Problem #4 19

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Problem #4 20

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Discussion #5 In this problem, the asynchronous inputs are used, but the FFs are configured synchronously (they each get their edges directly from the clock). The asynchronous inputs are active low. The FFs are configured in permanent Toggle mode. We must realize that the asynchronous inputs override the J, K and Clock inputs and affect the output state immediately. Also, there is an illegal input (an active input to both preset and reset). Problem #5 21

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Problem #5 22

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Discussion #6 This asynchronous configuration initially appears as a counter, but on closer examination you will note the different clock edges. The results is that this counter is neither an up or down counter, but a counter with a non-natural sequence count. The count pattern is: 1-6-7-4-5-2-3-0-1... Problem #6 23

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Problem #6 24

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END prgodin @ gmail.com 25

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