  Seattle Pacific University EE 1210 - Logic System DesignLatches-1 Feedback Circuits Two inverters, with feedback If the first input is 0, a 0 gets fed.

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 Seattle Pacific University EE 1210 - Logic System DesignLatches-1 Feedback Circuits Two inverters, with feedback If the first input is 0, a 0 gets fed back into it If the first input is 1, a 1 gets fed back into it This circuit will hold its state forever - stable 00 011 1

 Seattle Pacific University EE 1210 - Logic System DesignLatches-2 Changing the value How can we force this to be either ‘1’ or ‘0’? Replace one inverter with a tri-state inverter Add a tri-state inverter for input This is a simple one-bit memory cell. write in When write=‘1’, straight connection from input to output – We can write values in When write=‘0’, feedback connection – holds state out Add some control logic

 Seattle Pacific University EE 1210 - Logic System DesignLatches-3 Ring Oscillators Odd # of stages leads to ring oscillator Timing Waveform: 10 1 0 1 A B CD E F A B C D E F A and F are the same wire 0 10 1 0 1 0

 Seattle Pacific University EE 1210 - Logic System DesignLatches-4 Cross coupled NORs R S Q Qb S = set R = reset Q = output This is called an R-S Latch R S QQb 0 1 1 0 0 1 NOR: ‘0’ if either of its inputs are ‘1’ 0 1 0 1 1 0 1 0 1 1 0 0 0 0 ? ? 1 0 0 1 hold 0 0 When a NOR has one input at ‘0’, it inverts the other input When R and S are 0

 Seattle Pacific University EE 1210 - Logic System DesignLatches-5 Nors with R=S=1 Re-examine the inputs R=1 and S=1: What does it mean to both set and reset at the same time? R-S latch says “both lose!”  Q and Qb both are 0 What happens when R=S=1 (Q=Qb=0) and R or S changes to 0? S changes to zero first  Reset wins (Q=0, Qb=1) R changes to zero first  Set wins (Q=1, Qb=0) Both change at the same time to R=S=0… R S Q Qb 1 1 When R=S=1 changes to R=S=0, we get an uncontrolled oscillation (unstable) Moral of the story: R=S=1 is bad  Make it an illegal input 0 0 1 1 0 0 1 1 R S Q Qb 0 0

 Seattle Pacific University EE 1210 - Logic System DesignLatches-6 R-S Latch states SR’ S’R SR SR’ S’R+S’R’ == S’ S’R’+SR’ == R’ S’R’ SR+S’R’ SR’ S’R Q=0 Q=1 Q=0 Q=1 Q=0 R S QQ 0 1 10 1 0 01 0 0 holdhold 1 1 00 SR State: The current status of all memory elements. Changes to states occur only when inputs change All possible inputs must be “covered” by an arc out of each state

 Seattle Pacific University EE 1210 - Logic System DesignLatches-7 Using an R-S latch Design a system with two pushbuttons: Start and Stop Whenever Start is pushed, the signal Run will be asserted. Run should remain asserted until Stop is pushed. Start R S Run Stop GND +5 GND +5 R-S Latches are useful whenever a system should “remember” the last input

 Seattle Pacific University EE 1210 - Logic System DesignLatches-8 Switch Debouncing Out Ideal Out Actual Switch Depressed Switch Released Input GND +5 Out R S GND +5 Input GND

 Seattle Pacific University EE 1210 - Logic System DesignLatches-9 An enabled (gated) R-S latch R S Q Q R S Q Q Unclocked R-S Latch Clock Signal Output changes only when input changes, and enabled Level-sensitive R-S Latch R S Q Q R S En R S Q Q

 Seattle Pacific University EE 1210 - Logic System DesignLatches-10 Regular vs. Enabled R-S latches S R En Q (regular) Q (enabled) Enabled latch only changes when enable is asserted Reset Set Assume that latches have no time delay (ideal) R S Q Q En R S Q (enabled) R S Q Q R S Q (regular)

 Seattle Pacific University EE 1210 - Logic System DesignLatches-11 Clocking an enabled R-S Latch Clock (En) R Reset S Set Q A clocked R-S latch follows the R/S inputs when the clock is asserted. A clocked R-S latch stores the value when the clock goes low when the clock is not asserted. R S Q Q En Clock R S Q

 Seattle Pacific University EE 1210 - Logic System DesignLatches-12 D-Latches (gated) DQ C clk In a D-latch, the output follows the input when the clock is high. Clock D Q R S Q Q En D clk When the clock is low, the output remains what it was on the falling edge of the clock.

 Seattle Pacific University EE 1210 - Logic System DesignLatches-13 VHDL for D Latches (gated) LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY Dlatch IS PORT( D: INSTD_LOGIC; en : IN STD_LOGIC; Q : INOUTSTD_LOGIC); END Dlatch; ARCHITECTURE behavior OF Dlatch IS BEGIN PROCESS(D,en) BEGIN IF (en = ‘1’) THEN Q <= D; ELSE Q <= Q; END IF; END PROCESS; END behavior; Inputs: D and En Output: Q DQ en PROCESS list  State of latch can change due to a change in any of these values If enabled, Q  D If not enabled, Q keeps its old value Continuously monitors D and en looking for changes INOUT instead of OUT: Can be used as an input within the ENTITY

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