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IHP 2 Im Technologiepark Frankfurt (Oder) Germany IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Creation of SiGe Radhard Library AMICSA 2006 H.-V. Heyer 1, U. Jagdhold 2 Kayser-Threde GmbH 1 Wolfratshauser Str München Germany
IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Outline Introduction Goal Characterization of the Existing Technology New Layout Rules at Transistor Level New Design Rules at Design Level Outlook Example Local Oscillator (The SiMs and 30/20 Projects) Conclusion
IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Introduction I “High Frequency SiGe MMICs for Converter and Local Oscillators” (SiMs) survey demonstrates that the best candidate for optimal integration of microwave elements with high performance is the SiGe Technology (ESA TRP study) Microwave components (especially the Local Oscillator) for functional elements of communication equipments in space fit well with the performance to be achieved SiMs Study has identified IHP as best foundry for the SiGe components in up and down converters in space SiGe BiCMOS Technology is already a Radiation hard Technology according to Cressler ( Silicon-Germanium Heterojunction Bipolar Transistors, chapter 3 “SiGe HBT BiCMOS Technology”) Basic tests of the SGB25VD Technology shall demonstrate the Cressler statement (ESA ARTES 5 Programme)
IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Introduction II IHP is interested in the dedicated market for space and nuclear components market The RF experience needed is already existing from a lot of research projects Missing is radiation experience for IHP technology IHP has started a Radiation hardened Library Project to overcome this lack of experience This presentation will demonstrate the current und future activities of this project at IHP
IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Goal Radiation hardened components for the use in space projects as products in Multi-project-wavers MPW Radiation hardened components for the nuclear industry & research Radiation hardened library for SGB25VD Technology Radiation Hardness in the Level of 200 krad total dose Radiation Hardness by Design of the Transistors Layouts Radiation Hardness by Design Methods (e. g. Voter) No change in the existing Technology SGB25VD
IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Characterization of the Existing Technology I Characterization of the existing Technology is done in the following steps Characterization for very high dose rates and high dose levels (Mrad/s and 100Mrad total dose) Customers are the nuclear research facilities and their industries Test of basic structures, facility is CNM in Spain (Barcelona) Technology is already under tests Characterization for medium and low dose rates ( 2rad/s and 002rad/s up to 200Krad total dose) Customer is the space industry Test of basic structures within the 30/20 project (TID,SEE,NIEL tests), facility GfS Munich Germany, and RADEF Jyväskylä Finland
IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Characterization of the Existing Technology II Fig.1: Current Gain Degradation of Bipolar Transistors Radiation and Measurement done at CNM Barcelona
IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Characterization of the Existing Technology III Radiation test of the 30/20 Project Fig.2: Radiation Test Circuit Circuit Contains: Bipolar Transistors N-Mos Transistors P-Mos Transistors Bipolar Oscillator MOS Oscillator MOS Shiftregister Following Tests will be performed: Total Dose Test using Co60 up to 200krad Displacement Damage Test using proton beam up to protons/cm 2 Single Event Upset and Latchup Test using heavy ion beam ions/cm 2
IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Characterization of the Existing Technology IV Fig.3: Test Board with Bonded Chips and Wiring Fig.4: Test Equipment with Wiring
IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Characterization of the Existing Technology V Fig. 5: Schematic of the Local Oscillator Project 30/20, Radiation Hardness will be tested
IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Characterization of the Existing Technology VI New Test Chip will be made to characterize MIM`s, Interconnection, Resistors, and Diodes
IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved New Layout Rules at Transistor Level I New DRC Rules on Transistor Level Disabling of Latchup Rules is Forbidden Gate Poly extension of MOS gate is limited to max microns PWell and Nwell contact rings must have dimensions less than 12 microns All Devices must be located within contacted NWell/PWell Ring Gate Poly have not to cross any well border Gate Poly must be within NWell or Pwell Active Shapes on different nets must be shielded with well contact
IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved New Layout Rules at Transistor Level II Fig. 6: Radiation Hard Design Rule incorporation to DFII from Cadence
IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved New Layout Rules at Transistor Level III Fig.7: Inverter Design after new Radiation Hardness Rules after G. Anelli, Ref. Pwell + Contacts No Poly extensions over wells
IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved New Layout Rules at Transistor Level IV Fig. 8: Bipolar Transistor with PWell Ring and Contact Base Emitter Collector Pwell Ring with Ground Contact
IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved New Design Rules at Design Level I Cell Level: New Voter Cell Solution for Latch-up and Single Event Upset Drawback: Additional Area Input D Q > D Q > D Q > D Q > D Q > D Q > voter Output CLK Fig. 9: Voter Cell for Triple Module Redundancy after S. Habinc, Ref.
IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved New Design Rules at Design Level II System Level: Cache memory with parity protection Fig. 10: Cache with parity, Ref.  Solution for Latch-up, Single Event Upset Drawback: Additional Hardware parity generation parity generation FT memory (cache) exception (cache miss) parity check parity check memory controller
IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved New Design Rules at Design Level III Cell Level: IO corner cell with Latch-up detection System Level: Power down Latch_up detection Fig. 11: Latch up detector Solution for Latch-up Drawback: New Start of the Chip
IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Outlook I Example Local Oscillator (The SiMs and 30/20 Projects) Basic Structure radiation test schedule of 30/20
IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Outlook II Local Oscillator radiation test schedule of 30/20
IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Outlook III Start of New Project Radiation Hardness March 2006 Development of additional Test structures Oct Creation of a new CMOS Rad Hard Library Dec Design of a Rad Hard Test Device, e.g. Leon3ft Jan Preparation of the Test Device April 2007 Radiation Tests of the Test Device (in Cooperation)
IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Conclusion By using our inhouse BiCMOS Technology, it should be possible by applying new Design Rules and new Libraries to make circuits resistant against any kind of Radiation. Short Term: early access to Rad Hard Silicon Long Term: enclose a new market segment for IHP
IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Literature References  Giovanni Anelli, “Radiation-hard circuits in deep submicron CMOS technologies”, CERN, Microelectronics Group, Switzerland  Ulrich Trunk “Strahlenschäden in Integrierten Schaltungen” ASIC Labor Heidelberg, Physikalisches Institut der Universität Heidelberg, He Seminar, 2.Juli 2002,  Sandi Habinc, “Functional triple modular redundancy (FTMR) VHDL design methodology for redundancy in combinatorial and sequential logic” – Design and assessment report, Gaisler Research, Inc.
IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Physics Radiation: Leptonen, Bosonen, Baryonen, Mesonen Electrons, X-Ray, Protons, Neutrons, Alpha Particles, Heavy Ions… Energy: – 10 6 MeV Impact on Transistors: CMOS: Leakage of Transistors 1pA->1nA Drain Current change Bipolar: current gain degradation Impact on Circuitry: IC-Level Leakage, Latch-up, Single Event Upset Advantages: CMOS: for 0.25 micron Processes V t -Change no concern Bipolar: has already a guard ring, and there is always a current running through the device, Latch-up no concern
IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved Solution = Hardening by Design I Transistor Level: Guard Rings, Metal connection between Transistors many bulk contacts Solution for Latch-up, IC-Level Leakage Drawback: Area will be increased After G. Anelli, Ref. Folie von G. Schoof
IHP Im Technologiepark Frankfurt (Oder) Germany IHP Im Technologiepark Frankfurt (Oder) Germany ©
Experiment Electronics UMC 0.18µm radiation hardness studies Progress since last Collaboration Meeting Sven Löchner GSI Darmstadt 15 th CBM Collaboration.
Martin van Beuzekom 18 December LHCb Vertex Detector and Beetle Chip Outline: Introduction VErtex LOcator Pile-up trigger Radiation hardness of electronics.
Robert Szczygieł IFJ PANSPIE 2005 Radiation hardness of the mixed-mode ASIC’s dedicated for the future high energy physics experiments Introduction Radiation.
Experiment Electronics UMC 0.18µm radiation hardness studies - Update - Sven Löchner 13 th CBM Collaboration Meeting GSI Darmstadt March 12th, 2009.
Development of DC-DC converter ASICs S.Michelis 1,3, B.Allongue 1, G.Blanchot 1, F.Faccio 1, C.Fuentes 1,2, S.Orlandi 1, S.Saggini 4 1 CERN – PH-ESE 2.
Radiation Hardness Test Chip Matthias Harter, Peter Fischer Uni Mannheim.
First time common synthesis and simulation of ECL and CMOS parts at a BiCMOS chip based on the IHP SGB25V Library Frank Winkler, Humboldt University of.
IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved IHP Technology Roadmap Update and Future.
10 CBM Collaboration Meeting 2007 Sept Moscow Engineering Physics Institute (State University) Status of Radiation Tolerant Blocks for STS A.
SAAB SPACE 1 The M2 ASIC A mixed analogue/digital ASIC for acquisition and control in data handling systems Olle Martinsson AMICSA, October 2-3, 2006.
MAPLD 2005/213Kakarla & Katkoori Partial Evaluation Based Redundancy for SEU Mitigation in Combinational Circuits MAPLD 2005 Sujana Kakarla Srinivas Katkoori.
1 Radiation tolerance of commercial 130nm CMOS technologies for High Energy Physics Experiments Federico Faccio for the CERN(PH/MIC)-DACEL * collaboration.
Investigating latchup in the PXL detector Outline: What is latchup? – the consequences and sources of latchup – techniques to reduce latchup sensitivity.
1 Radiation tolerance of commercial 130nm technologies for High Energy Physics Experiments Federico Faccio CERN/PH-MIC.
11-1 Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon Latch-up & Power Consumption Latch-up Problem Latch-up condition 1 2 >1 GND Vdd.
1 Single event upset test of the voltage limiter for the ATLAS Semiconductor tracker TSL Experiment Number: F151 distance between power supplies and modules.
Motivation for 65nm CMOS technology - Benefits - Higher density, less material - Power - Enhanced radiation hardness regular layout) - Extensive existing.
R. Kass US LC Conference 1 Design and Fabrication of a Radiation-Hard 500-MHz Digitizer Using Deep Submicron Technology R. Kass The Ohio State University.
Space Radiation and Fox Satellites 2011 Space Symposium AMSAT Fox.
Process Monitor/TID Characterization Valencia M. Joyner.
Radiation Tolerance D. C. Christian, J. A. Appel, G. Chiodini,
1 VLSI Digital System Design Input-Output Pads. 2 Input-Output Pad Design I-O pad design is highly specialized –Requires circuit design experience –Requires.
NMOS FABRICATION 1. Processing is carried out on a thin wafer cut from a single crystal of silicon of high purity into which the required p-impurities.
1 Sachs et. al. IEEE Trans. Nuclear Science NS-31, 1249 (1984) Threshold Shift vs Gate Oxide Thickness Hole removal process by tunneling in thin-oxide.
KIT – Universität des Landes Baden-Württemberg und nationales Forschungszentrum in der Helmholtz-Gemeinschaft KIT, Institut für Prozessdatenverarbeitung.
Digital Integrated Circuits© Prentice Hall 1995 Devices Jan M. Rabaey The Devices.
Progress on Radiation Hardness Tests on SiGe Technologies for S-LHC Miguel Ullán, F. Campabadal, S. Díez, C. Fleta, M. Lozano, G. Pellegrini, J. M. Rafí.
A Novel, Highly SEU Tolerant Digital Circuit Design Approach By: Rajesh Garg Sunil P. Khatri Department of Electrical and Computer Engineering, Texas A&M.
Eija Tuominen Siena TEST BEAM RESULTS OF A LARGE AREA STRIP DETECTOR MADE ON HIGH RESISTIVITY CZOCHRALSKI SILICON Helsinki Institute of Physics,
Design Methodology for highly Reliable Digital ASIC Designs Dr. Ing. Vladimir Petrovic
1 VLSI Fabrication Technology. Microelectronic Circuits - Fifth Edition Sedra/Smith2 Copyright 2004 by Oxford University Press, Inc. Figure A.1 Silicon.
Barrel EM Calorimeter Preamp / Shaper Update Mitch Newcomer, Andrew Townley Prepared for Munich Liquid Argon Week 2011.
Purpose of design rules: Design Rules Interface between designer and process engineer Guidelines for constructing process masks – Minimum width – Minimum.
Analog VLSI Design Nguyen Cao Qui. Introduction to the course Name: “ Analog VLSI Design ” Instructor: Nguyen Cao Qui
Lab 1: To generate layout for CMOS Inverter circuit and simulate it for verification.
E.N. Spencer SCIPP-UCSC ATLAS 13-September-05 1 SiGe biCMOS for Next Gen Strip Readout 1 Evaluation of SiGe biCMOS Technologies for Next Generation Strip.
Evaluation of 65nm technology for front-end electronics in HEP Pierpaolo Valerio 1 Pierpaolo Valerio -
COTS Regulator Studies Derek Donley*, Mitch Newcomer, Mike Reilly *Hospital of the University of Pennsylvania, Radiation Oncology.
Chapter 2: Fundamentals of Digital Electronics Dr Mohamed Menacer Taibah University
A.Marchioro - CERN/PH1 Accessing 130 nm CMOS Tech for ILC (Public Version) Oct 2006, Munich A. Marchioro CERN, Div. PH 1211 Geneva 23, Switzerland.
The development of the readout ASIC for the pair-monitor with SOI technology ~irradiation test~ Yutaro Sato Tohoku Univ. 29 th Mar Introduction.
A 30 GS/s 4-Bit Binary Weighted DAC in SiGe BiCMOS Technology Halder, Samiran and Gustat, Hans IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2007.
Radiation Tests on IHP’s SiGe Technologies for the Front-End Detector Readout in the S-LHC M. Ullán, S. Díez, F. Campabadal, G. Pellegrini, M. Lozano CNM.
VLSI, Lecture 1 A review of microelectronics and an introduction to MOS technology Department of Computer Engineering, Prince of Songkla.
SEU tolerant cells developed for the FEI4 chip Patrick Breugnon, Denis Fougeron, Mohsine Menouni, Alexandre Rozanov CPPM-CNRS-Université de la mediterranée-Marseille.
Technology Overview or Challenges of Future High Energy Particle Detection Tomasz Hemperek
Danish Space Research Institute Danish Small Satellite Programme FH Space_Environment.ppt Slide # 1 Flemming Hansen MScEE, PhD Technology Manager.
For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002.
Latch-Up and its Prevention Latch is the generation of a low- impedance path in CMOS chips between the power supply and the ground rails due to interaction.
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