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VLSI System Design Lecture: 1.6 Tri-states, Mux, Latches & Flip Flops Engr. Anees ul Husnain ( Department.

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Presentation on theme: "VLSI System Design Lecture: 1.6 Tri-states, Mux, Latches & Flip Flops Engr. Anees ul Husnain ( Department."— Presentation transcript:

1 VLSI System Design Lecture: 1.6 Tri-states, Mux, Latches & Flip Flops Engr. Anees ul Husnain ( anees.buzdar@gmail.com )anees.buzdar@gmail.com Department of Computer Systems Engineering, College of Engineering & Technology, IUB

2 Compound Gates recall…  Y = ( A + B + C )Y = ( A. B. C )??  CMOS compound gate for function Y = (A B) + (C D) ???

3 Example: O3AI  Y = (A + B + C ). D

4 TRISTATES… Buffer & Pass Gate When the enable input EN is '1,' the output Y equals the inputs, just as in an ordinary buffer. When the enable is '0,' Y is left floating (a 'Z' value). The transmission gate in Figure 1.25 has the same truth table as a tri-state buffer. It only requires two transistors but it is a non- restoring circuit. ENAY 00Z 01Z 100 111

5 Transmission Gate Buffer… If the input is a noisy or other-wise degraded signal, the output will receive the same noise. After several stages of non restoring logic, a signal can become too degraded to recognize. Does fully restored CMOS with a noisy input degrade the output?? (a) shows a tri-state inverter. The output is actively driven from VDD or GND, so it is a restoring logic gate. Unlike any of the gates considered so far, the tri-state inverter does not obey the conduction complements rule because it must allow the output to float under certain input combinations.

6 Transmission Gate Buffer… The Enable key & The Floating State When EN is '0' (Fig (b)), both enable transistors are OFF, leaving the output floating. When EN is '1' (Fig (c)), both enable transistors are ON. They are conceptually removed from the circuit, leaving a simple inverter.

7 Multiplexers… A multiplexer chooses the output to be one of several inputs based on a select signal. A two-input, or 2:1 multiplexer, chooses input D0 when the select is '0' and input D1 when the select is ‘1‘. The logic function is Y=SD0+SDl. SD1D0Y 0X00 0X11 10X0 11X1

8 Gate-Level Multiplexer Design   How many transistors are needed? 20

9 Transmission Gate Multiplexer … Two transmission gates can be tied together to form a compact 2- input multiplexer, as shown in Figure 1.27(a) Again, the transmission gates produce a non-restoring multiplexer. We could build a restoring, inverting multiplexer out of gates in several ways. BUT... WHAT IF SELECT IS ‘X’ ???

10 Restoring CMOS Multiplexer … Several ways… One: The compound gate of connected as shown in Fig (a). Another: Another is to gang together two tri-state inverters, as shown in Fig (b). The tri-state approach is slightly more compact and faster because it requires less internal wire. Larger multiplexers can be built from multiple 2-input multiplexers or by directly ganging together several tri-states.

11 4:1 Multiplexer  4:1 mux chooses one of 4 inputs using two selects Two levels of 2:1 muxes Or four tristates

12 Latches & Flip Flops A D-latch A 2-input multiplexer & 2 inverters

13 Latches & Flip Flops A D-latch When CLK=‘1,' the latch is transparent. Q = D and Q = D fig (c) When CLK" is switched to '0,' the latch is opaque. A feedback path around the inverter pair is established (d) to hold the current state of Q indefinitely.

14 Latches & Flip Flops A D-latch  The D latch is also known as a level-sensitive latch because the state of the output is dependent on the level of the clock signal, as shown in Fig(e).  The latch shown is a positive-level-sensitive latch, represented by the symbol in Fig (f). By inverting the control connections to the multiplexer, a negative-level-sensitive latch may be constructed.

15 Latches & Flip Flops D flip flop By combining two level-sensitive latches, one positive- sensitive and one negative-sensitive, we construct an edge-triggered flip-flop as shown in Figs. By convention, the first latch stage is called the master and the second is called the slave.

16 Latches & Flip Flops A D Flip Flop  While CLK is low, the master negative-level-sensitive latch output (QM) follows the D input while the slave positive-level-sensitive latch holds the previous value (Fig(c)).  When the clock transitions from 0 to 1, the master latch ceases to sample the input and holds the D value at the time of the clock transition.

17 Latches & Flip Flops A D Flip Flop

18 Latches & Flip Flops Class Activity  Make a D flip flop with Negative Level Sensitive Master Latch

19 Latches & Flip Flops Class Activity  From the Flip Flop pass the following inputs to find output Q ?

20 Race Condition  Back-to-back flops can malfunction from clock skew Second flip-flop fires late Sees first flip-flop change and captures its result Called hold-time failure or race condition

21 Nonoverlapping Clocks  Non-overlapping clocks can prevent races As long as non-overlap exceeds clock skew  We will use them in this class for safe design Industry manages skew more carefully instead

22 Next…  Layout Design  Stick Diagrams


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