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Joachim Schultes University of Wuppertal Interlock System DCS Training Session 2.3.

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Presentation on theme: "Joachim Schultes University of Wuppertal Interlock System DCS Training Session 2.3."— Presentation transcript:

1 Joachim Schultes University of Wuppertal Interlock System DCS Training Session 2.3

2 DCS Training 2007: Interlock SystemJoachim Schultes Overview Interlock System StructureStructure NumbersNumbersComponents BBIM (Temperature Interlock, see session 1)BBIM (Temperature Interlock, see session 1) PP1 Box (Laser Interlock)PP1 Box (Laser Interlock) BOC-I-Box (Laser Interlock)BOC-I-Box (Laser Interlock) Logic UnitsLogic Units Interlock Distribution BoxInterlock Distribution Box

3 DCS Training 2007: Interlock SystemJoachim Schultes Interlock System (ATL-IP-ES-0110) TemperatureInterlock LaserInterlock

4 DCS Training 2007: Interlock SystemJoachim Schultes Overview of Interlock System

5 DCS Training 2007: Interlock SystemJoachim Schultes User Interface and common User Interface Shortcut on desktop (preferred)Shortcut on desktop (preferred) Additional manager inside the PVSS consoleAdditional manager inside the PVSS console Device Editor Navigator Use of the logical tabUse of the logical tab Click on the entry opens the corresponding panelsClick on the entry opens the corresponding panels General on Interlock Boxes: Channels are latchedChannels are latched Reset: reset the latches (preferred)Reset: reset the latches (preferred) Transparent: no latching (debugging)Transparent: no latching (debugging) Colour code for each monitored output channelColour code for each monitored output channel Test signals for debuggingTest signals for debugging

6 DCS Training 2007: Interlock SystemJoachim Schultes Laser Safety: PP1-Box and BOC-I-Box BOC-I-Box (one) InputsInputs 5 door switches of the Readout Racks5 door switches of the Readout Racks 2 x 4 I PP1 signals of PP1-Box2 x 4 I PP1 signals of PP1-Box Interlock signals forInterlock signals for 5 x 1 I BOC signal for the two BOC crates inside the readout racks (local)5 x 1 I BOC signal for the two BOC crates inside the readout racks (local) I PP1 signals for the two BOC crates inside the readout racks (remote)I PP1 signals for the two BOC crates inside the readout racks (remote) 5 I BOC signals for PP1-Box and LU5 I BOC signals for PP1-Box and LU PP1-Box (one per counting room) inputsinputs I DSS (ATLAS Detector Safety System)I DSS (ATLAS Detector Safety System) 8 signals from PP1 micro switches8 signals from PP1 micro switches Interlock signals forInterlock signals for 4 I PP1 signals for 14 LU (SC-OLink)4 I PP1 signals for 14 LU (SC-OLink)

7 DCS Training 2007: Interlock SystemJoachim Schultes User interface for PP1-Box and BOC-I-Box BOC-I-Box (one) Signals of 5 door switches from readout racksSignals of 5 door switches from readout racks 5 I BOC signals to PP1-Box5 I BOC signals to PP1-Box 2 x 4 I PP1 signals from PP1-Box (US and USA)2 x 4 I PP1 signals from PP1-Box (US and USA) PP1-Box (one per counting room) 8 I PP1 signals from PP1 switches8 I PP1 signals from PP1 switches 4 I PP1 outputs to BOC-I-Box4 I PP1 outputs to BOC-I-Box 5 I BOC signals from BOC-I-Box5 I BOC signals from BOC-I-Box 1 I DSS signal1 I DSS signal Channels are latchedChannels are latched Reset: reset the latches (preferred)Reset: reset the latches (preferred) Transparent: no latching (debugging)Transparent: no latching (debugging)

8 DCS Training 2007: Interlock SystemJoachim Schultes Logic Unit one per Regulator Station (12 read out units)one per Regulator Station (12 read out units) ComponentsComponents FPGA-BlockFPGA-Block 1 FPGA board1 FPGA board 1 Wupp-ELMB1 Wupp-ELMB 2 Latch boards2 Latch boards 3 T-Module blocks3 T-Module blocks 1 Wupp-ELMB1 Wupp-ELMB 2 Latch boards2 Latch boards 12 identical I-Matrix elements12 identical I-Matrix elements

9 DCS Training 2007: Interlock SystemJoachim Schultes I-Matrix element of the Logic Unit InputsInputs 6(7) x I T_modules  1 x I T_high6(7) x I T_modules  1 x I T_high 1 x I T_optoboard1 x I T_optoboard 7 x I T_PP27 x I T_PP2 1 x I DSS1 x I DSS 1 x I BOC1 x I BOC 1 x I PP11 x I PP1 OutputsOutputs 1 x I HV1 x I HV 1 x I LV_Vdda / I LV_Vdd1 x I LV_Vdda / I LV_Vdd 1 x I SC-OLink1 x I SC-OLink

10 DCS Training 2007: Interlock SystemJoachim Schultes User interface for Logic Unit Monitors input signals (dots)Monitors input signals (dots) Channels are latchedChannels are latched Reset: reset the latches (preferred)Reset: reset the latches (preferred) Transparent: no latching (debugging)Transparent: no latching (debugging) Disconnected status without InterlockDisconnected status without Interlock A good possibility to recognize disabled channels Interlock Disabled channels (dipp switches) disconnected Interlock FPGA reset

11 DCS Training 2007: Interlock SystemJoachim Schultes Disabling of interlock channels inside the logic unit Reasons for disabling of interlock channelsReasons for disabling of interlock channels Different modularity (6 or 7 modules)Different modularity (6 or 7 modules) Broken sensors or cableBroken sensors or cable Temperature interlock of regulator stations (I PP2 )Temperature interlock of regulator stations (I PP2 ) 1 dip switches for the 7 temperature sensors inside PP21 dip switches for the 7 temperature sensors inside PP2 Individual FPGA program of Logic unitIndividual FPGA program of Logic unit 1 dip switch for adressing1 dip switch for adressing Temperature interlock of modules (I Tmodule )Temperature interlock of modules (I Tmodule ) 12 dip switches for the 12 read out units12 dip switches for the 12 read out units

12 DCS Training 2007: Interlock SystemJoachim Schultes Interlock Distribution Box: HV, LV and SC-OLink Interlock Distribution Box: Aim: flexible mapping of Interlock signals to power supply channelsAim: flexible mapping of Interlock signals to power supply channels Inputs for signals of 7 LU (72 channels due to configuration)Inputs for signals of 7 LU (72 channels due to configuration) Channels are latchedChannels are latched Reset: reset the latches (preferred)Reset: reset the latches (preferred) Transparent: no latching (debugging)Transparent: no latching (debugging)IDB-HV Responsible for 5 iseg modulesResponsible for 5 iseg modules 5 x (2 x 8) Outputs5 x (2 x 8) OutputsIDB-LV Responsible for 6 Wiener cratesResponsible for 6 Wiener crates 6 x 12 Outputs6 x 12 OutputsIDB-SC-OLink Responsible for 5 SC-OLink cratesResponsible for 5 SC-OLink crates 5 x (4 x 4) Outputs5 x (4 x 4) Outputs


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