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Register vs Latch vs SRAM

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Delay vs. Drive Strength Cell Area rise_delay fall_delay inv_a ps 192ps inv_a ps 140ps inv_a ps 100ps nand2_a ps 228ps nand2_a ps 166ps nor2_a ps 173ps nor2_a ps 123ps

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Distribution of Gates (DMA) Leaf Cell: Count: Area: and2_a and2_a and3_a and3_a aoi21_a aoi21_a aoi22_a aoi22_a buf_a buf_a buf_a inv_a inv_a inv_a muxi2_a muxi2_a nand2_a nand2_a nand2_a nand3_a nand4_a nor2_a nor2_a nor3_a nor3_a nor4_a oai21_a oai21_a oai22_a oai22_a or2_a or2_a or3_a or3_a w_and2_a w_and3_a w_aoi21_a w_buf_a w_buf_a w_dff0_a w_dff1_a w_inv_a w_inv_a w_inv_a w_muxi2_a w_nand3_a w_nand3_a w_nand4_a w_nand4_a w_nor2_a w_nor3_a w_nor4_a w_oai21_a w_oai22_a w_or2_a w_or3_a w_sbuf_a w_sbuf_a w_sbuf_a w_sinv_a w_sinv_a w_sinv_a xnor2_a xnor2_a xor2_a xor2_a xor2_a

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Static Timing Analysis (DMA) Startpoint: dp_rx_pkt_adr_ff_reg_1A (rising edge-triggered flip-flop clocked by clk) Endpoint: dp_rx_pkt_adr_ff_reg_25A (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Point Incr Path clock clk (rise edge) clock network delay (ideal) dp_rx_pkt_adr_ff_reg_1A/CK (w_dff1_a2) r dp_rx_pkt_adr_ff_reg_1A/Q (w_dff1_a2) r U6194/Q (w_sbuf_a8) r U8354/Q (nand2_a4) f U8691/Q (inv_a4) r U8455/Q (nand2_a4) f U8619/Q (inv_a2) r U8355/Q (nand2_a4) f U4974/Q (inv_a2) r U8454/Q (nand2_a4) f U8618/Q (inv_a2) r U8356/Q (nand2_a4) f U8692/Q (inv_a4) r U3181/Q (and2_a2) r U8364/Q (nand2_a4) f U8693/Q (inv_a4) r U2029/Q (and2_a2) r U6366/Q (nand2_a1) f U6367/Q (inv_a2) r U3183/Q (and2_a2) r U6364/Q (and2_a1) r U8459/Q (nand2_a4) f U8622/Q (inv_a2) r U6365/Q (and2_a1) r U8360/Q (nand2_a4) f U2034/Q (w_or2_a4) f U8621/Q (inv_a2) r U6362/Q (nand2_a1) f U6363/Q (inv_a2) r U8458/Q (nand2_a4) f U8620/Q (inv_a2) r U6360/Q (nand2_a1) f U6361/Q (inv_a2) r U2038/Q (and2_a2) r U6358/Q (nand2_a1) f U6359/Q (inv_a2) r U8457/Q (nand2_a4) f U5187/Q (inv_a1) r U6356/Q (nand2_a1) f U6357/Q (inv_a2) r U8456/Q (nand2_a4) f U8395/Q (w_nor2_a4) r U8476/Q (xor2_a2) f U8094/Q (nand2_a1) r U8633/Q (w_nand3_a4) f dp_rx_pkt_adr_ff_reg_25A/D (w_dff1_a2) f data arrival time 3.50 clock clk (rise edge) clock network delay (ideal) clock uncertainty dp_rx_pkt_adr_ff_reg_25A/CK (w_dff1_a2) 5.45 r library setup time data required time data required time 5.36 data arrival time slack (MET) 1.86

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