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Register vs Latch vs SRAM. Delay vs. Drive Strength Cell Area rise_delay fall_delay inv_a1 9.4 318ps 192ps inv_a4 15.68 241ps 140ps inv_a8 47.04 200ps.

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Presentation on theme: "Register vs Latch vs SRAM. Delay vs. Drive Strength Cell Area rise_delay fall_delay inv_a1 9.4 318ps 192ps inv_a4 15.68 241ps 140ps inv_a8 47.04 200ps."— Presentation transcript:

1 Register vs Latch vs SRAM

2 Delay vs. Drive Strength Cell Area rise_delay fall_delay inv_a1 9.4 318ps 192ps inv_a4 15.68 241ps 140ps inv_a8 47.04 200ps 100ps nand2_a1 12.54 375ps 228ps nand2_a4 28.22 207ps 166ps nor2_a1 12.54 440ps 173ps nor2_a4 28.22 338ps 123ps

3 Distribution of Gates (DMA) Leaf Cell: Count: Area: and2_a1 642 6214.5600 and2_a2 42 487.8720 and3_a1 131 1521.6960 and3_a2 13 201.3440 aoi21_a1 180 1742.4000 aoi21_a2 15 290.4000 aoi22_a1 315 3659.0400 aoi22_a2 9 209.0880 buf_a1 130 1006.7200 buf_a2 350 3388.0000 buf_a4 295 4568.9600 inv_a1 1371 7962.7680 inv_a2 391 3027.9040 inv_a4 443 5145.8880 muxi2_a1 261 4042.3680 muxi2_a2 22 425.9200 nand2_a1 811 6280.3840 nand2_a2 247 2869.1520 nand2_a4 105 2236.0800 nand3_a1 64 619.5200 nand4_a1 88 1022.2080 nor2_a1 587 4545.7280 nor2_a2 94 1091.9040 nor3_a1 26 251.6800 nor3_a2 9 174.2400 nor4_a2 14 433.6640 oai21_a1 142 1374.5600 oai21_a2 62 1200.3200 oai22_a1 31 360.0960 oai22_a2 5 116.1600 or2_a1 232 2245.7600 or2_a2 53 718.2560 or3_a1 74 1002.8480 or3_a2 1 25.1680 w_and2_a4 52 1208.0640 w_and3_a4 3 92.9280 w_aoi21_a4 3 116.1600 w_buf_a16 14 758.9120 w_buf_a8 27 731.8080 w_dff0_a2 221 9412.8320 w_dff1_a2 1054 57135.2320 w_inv_a16 13 553.6960 w_inv_a32 1 81.3120 w_inv_a8 74 1719.1680 w_muxi2_a4 5 193.6000 w_nand3_a2 16 309.7600 w_nand3_a4 5 174.2400 w_nand4_a2 81 1881.7920 w_nand4_a4 3 127.7760 w_nor2_a4 112 2601.9840 w_nor3_a4 1 38.7200 w_nor4_a4 3 185.8560 w_oai21_a4 25 968.0000 w_oai22_a4 5 251.6800 w_or2_a4 19 514.9760 w_or3_a4 2 100.6720 w_sbuf_a16 5 271.0400 w_sbuf_a32 10 968.0000 w_sbuf_a8 88 2385.1520 w_sinv_a16 137 5835.1040 w_sinv_a32 102 8293.8240 w_sinv_a8 119 2764.6080 xnor2_a1 116 2021.1840 xnor2_a2 67 1686.2560 xor2_a1 113 1968.9120 xor2_a2 240 6040.3200 xor2_a4 2 58.0800

4 Static Timing Analysis (DMA) Startpoint: dp_rx_pkt_adr_ff_reg_1A (rising edge-triggered flip-flop clocked by clk) Endpoint: dp_rx_pkt_adr_ff_reg_25A (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Point Incr Path --------------------------------------------------------------- clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 dp_rx_pkt_adr_ff_reg_1A/CK (w_dff1_a2) 0.00 0.00 r dp_rx_pkt_adr_ff_reg_1A/Q (w_dff1_a2) 0.31 0.31 r U6194/Q (w_sbuf_a8) 0.10 0.41 r U8354/Q (nand2_a4) 0.06 0.47 f U8691/Q (inv_a4) 0.04 0.51 r U8455/Q (nand2_a4) 0.05 0.56 f U8619/Q (inv_a2) 0.06 0.62 r U8355/Q (nand2_a4) 0.05 0.67 f U4974/Q (inv_a2) 0.06 0.73 r U8454/Q (nand2_a4) 0.05 0.78 f U8618/Q (inv_a2) 0.06 0.84 r U8356/Q (nand2_a4) 0.05 0.90 f U8692/Q (inv_a4) 0.04 0.93 r U3181/Q (and2_a2) 0.12 1.05 r U8364/Q (nand2_a4) 0.05 1.11 f U8693/Q (inv_a4) 0.04 1.14 r U2029/Q (and2_a2) 0.10 1.24 r U6366/Q (nand2_a1) 0.07 1.31 f U6367/Q (inv_a2) 0.05 1.36 r U3183/Q (and2_a2) 0.11 1.48 r U6364/Q (and2_a1) 0.19 1.66 r U8459/Q (nand2_a4) 0.07 1.74 f U8622/Q (inv_a2) 0.03 1.77 r U6365/Q (and2_a1) 0.18 1.95 r U8360/Q (nand2_a4) 0.07 2.02 f U2034/Q (w_or2_a4) 0.12 2.15 f U8621/Q (inv_a2) 0.03 2.18 r U6362/Q (nand2_a1) 0.06 2.24 f U6363/Q (inv_a2) 0.08 2.32 r U8458/Q (nand2_a4) 0.06 2.38 f U8620/Q (inv_a2) 0.03 2.41 r U6360/Q (nand2_a1) 0.06 2.47 f U6361/Q (inv_a2) 0.05 2.52 r U2038/Q (and2_a2) 0.11 2.63 r U6358/Q (nand2_a1) 0.07 2.69 f U6359/Q (inv_a2) 0.08 2.77 r U8457/Q (nand2_a4) 0.06 2.83 f U5187/Q (inv_a1) 0.05 2.88 r U6356/Q (nand2_a1) 0.06 2.94 f U6357/Q (inv_a2) 0.08 3.02 r U8456/Q (nand2_a4) 0.07 3.09 f U8395/Q (w_nor2_a4) 0.06 3.15 r U8476/Q (xor2_a2) 0.15 3.31 f U8094/Q (nand2_a1) 0.09 3.39 r U8633/Q (w_nand3_a4) 0.11 3.50 f dp_rx_pkt_adr_ff_reg_25A/D (w_dff1_a2) 0.00 3.50 f data arrival time 3.50 clock clk (rise edge) 5.80 5.80 clock network delay (ideal) 0.00 5.80 clock uncertainty -0.35 5.45 dp_rx_pkt_adr_ff_reg_25A/CK (w_dff1_a2) 5.45 r library setup time -0.09 5.36 data required time 5.36 ----------------------------------------------------------- data required time 5.36 data arrival time -3.50 ----------------------------------------------------------- slack (MET) 1.86


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