Presentation on theme: "EECS 465: Digital Systems Lecture Notes # 7"— Presentation transcript:
1 EECS 465: Digital Systems Lecture Notes # 7 (A) Introduction to Sequential Circuits(B) Latches and Flip-Flops(C) Counter DesignSHANTANU DUTTDepartment of Electrical and Computer EngineeringUniversity of Illinois, ChicagoPhone: (312) :URL:
2 (A) Introduction to Sequential Circuits • Current o/p depends on the current i/p and past history of all i/psseen by the circuit.Where the relevant past history should be representable by a finitenumber of classes or statesLight = GreenO/P = 1Light = Not redO/P = 0ResetNo RedRed LightStateEncode asstate = 1Light = RedO/P = 0Light = Not greenO/P = 0Encode as state=0State Transition DiagramDesign Problem: Output of the circuit is 1 only if it has seen a redlight in the past and currently light is green.
3 Circuit-Level Model of a Sequential Circuit. I/p fromexternalpointx0Z0Going toexternalworldCombinationalCircuitxn-1Zm-1Statebits ofseq. ckt.yk-1y’k-1y0y’0MemoryUnitNextStateCurrentState
4 (B) Latches and Flip-Flops Components to store bits ( latches or flip flops )1)Problem: can’t storenew data111Cascade of inverterLD2)I/P1/0O/PLDAWill conduct whenA=1, and open whenA=0
5 Another storage element: NOR gates ( R-S latch ) 3) Cross coupled NOR gates ( R-S latch )(Reset)RQSQQ1R=0S=1(Set)BProperty of a NOR gateA=0When one I/P of NOR is 0, it acts like an inverter.When one I/P is 1, then O/P=0.Different I/P conditions for R-S latch:i) R=S=0, current I/P is stored indefinitely( becomes cascade of inverters)Hold
6 ii) R=1, S=0, when we want to store a 0 in the R-S latch. Q=0, iii) R=0, S=1, when we want to store a 1 in the latch.Q=1,iv) R=1, S=1; Forbidden inputs!Both Q = 0, : Q and its complement have the same value !Will play havoc in the rest of the logic circuit.Transit to: R=0, S=0.R=1, S=1, both Q and and 0.O/P oscillates.QR=10S=101010Oscillatesbetween 1 and 0when we transit fromR=S=1 to R=S=0.
7 From R, S = 1, 1 transit to R=0, S=1 then Q, transit to 1, 0 ( correctly )From R, S = 1, 1 transit to R=1, S=0then Q, correctly transit to 0, 1Two implementations for R-S latch:Cross-coupled NORCross-coupled NANDRQSRSQHold State R=S=1Hold State R=S=0R=0, S=0R=1, S=1QForbidden I/Ps
8 (level-sensitive clock latch) — see terminology defined later. 4) The D-LatchRR1QR-SLatchClocked Latch(level-sensitive clock latch)— see terminology definedlater.enbDS1SD=1, S=1, R=0Q=1,D=0, S=0, R=1Q=0,enb=0 R1,S1=0 (hold state)enb=1enb=1
9 — Proposed to get rid of the forbidden I/P problem of R-S 5) The J-K Latch:— Proposed to get rid of the forbidden I/P problem of R-Si) J=1, K=0: (a) Let Q=1, R=0,S=0 Hold state of R-S Q=1,(b) Let Q=0, , R=0, S=1 Q=1,ii) J=0, K=1 Q=0, using a similar analysisiii) J=K=0 Hold stateiv) J=K=1, suppose Q=1, =0 R=1, S=0 Q=0, =1 S=1, R=0 Q=1, =0This type of toggling continues as long as J=K=1, and the latchis enabled ( CLK=1 below )Q1010RKRCLKR-SJ1SQ0101
10 Latch classification with respect to response to “control signal” Terminology: Note that the terminology below applies to all types of latches:R-S, D, J-K, T, etc., though the examples are given for the R-S latch.i) Transparent Latch: O/P responds to latch I/Ps without any enable or clock signal.RQSSymbol:RSQClock:Fixed frequency alternating 1 and 0 signalii) Clocked or Level-Sensitive Latch:RO/P responds to I/Ps only when enb orclock is at a pre-determined level (highor low — In this example, it is High)QClockorenbSSymbol:RSQRSQorCLK(low enable)(high enable)CLK
11 iii) Edge-Triggered Flip-Flop (FF) or simply Flip-Flop O/P will respond to I/Ps only at either:(a) the positive or rising edge of the enb/clock signal (positiveedge-triggered FF), or(b) the negative or falling edge of the enb/clock signal (negativeedge-triggered FF).Symbol:RQSCLKSymbol:RSQCLKClock:O/P resp. period fora low-enable/clocklevel sensitive latchO/P responseperiod for apositiveedge-triggeredFF.O/P responseperiod for aHIGH-enable/clocklevel-sensitivelatchO/P responseperiod for anegativeedge-triggeredFF
12 Setup Times and Hold Time of FFs and Latches • Assume, positive edge-triggered D-FFTHold relates to propagation delayof another part of circuit.DCLKTSetup relates to propagation delays ofvarious gates in the FF.The high point ofthe CLK determines the positive edge’s arrival.• If negative edge-triggeredTSetupTHoldDCLKNegative edge arrival• If D-Latch is high-level sensitive: Tsetup and Thold have to be around the negative edgeof clock (more specifically, when the clock begins to go low), similar to negative edge-triggered.•If D-Latch is low-level sensitive: Tsetup and Thold have to be around the positiveedge of clock, similar to positive edge-triggered.
13 Solutions to Race Condition Problem with Level Sensitive Latches Solution 1: Master-Slave FF:Q1RR-SLatchJR111R-SPQmKQsSSQCLKMaster R-S is level sensitive.Slave R-S is level sensitive.Master-Slave J-K is a solution to race-condition problem: Any change in Q,during CLK=0 is not propagated to P, and hence back to Q, during thesame CLK=0. Any change to Q, will occur in next CLK=0 period.JQJ-KM-SMaster-Slave J-K works similarto a J-K latch: E.g. LetJ=1, K=1, CLK=1Q=1, =0 =1 , P=0When CLK=0Q=0, =1K(O/P responds when CLK goesFrom 1 to 0)
14 Solution 2: Edge-Triggered FF: Assume D=1D=1=SQ=1,Solution 2: Edge-Triggered FF:DHolds whenclock goes lowRQ =DClk=0RQSClk=1DQ responds tointernal S signal;responds tointernal R signal.SDHolds D whenclock goes lowDCLKDWhen CLK is 1 D I/P isinternally sampled butdoes not appear at the O/P.O/P appears (Q=D)RQO/P is held (changing D does notcause any change in internalsignals in the FF or in its output)Clk=0SDD
15 Characteristic Equations of Latches/FFs The next O/P Q+ defined in terms of the current O/P Q and the I/P.(FF/Latch is the simplest possible sequential ckt.)1) R-S Latch— Truth Table:Values at time tS(t) R(t) Q(t) Q+ = Q( t+ )xxHoldResetSetForbiddenQ+= S+ Q(Characteristic equation)Q(t)\SRxx
16 Similarly: Characteristic Equations of 2) J-K, Q+ = Q + J. 3) D-FF, Q+ = D4) Toggle FF/Latch Q+ = T + Qor T-FF / LatchSymbol:QTWhenever I/P T is high,the FF will toggle, i.e., Q+ = .When T=0, Q+=Q.Of course, these characteristic equations come into play onlywhen the FF/Latch is enabled.
17 Excitation Table— Reversed Truth Table— What the inputs to FFs should be for given outputtransitions (Q Q+)Q Q+ R S J K T Dx xxxx x
18 — Conversion between FFs Example: J-K to D This shouldbehave like aD-FF.JKQDCLKLogicDDx x1QDQO/P function = JJ=DFunction = KK=x xMap the D,Q input combination to a QQ+ transitionand then map this to J-K excitation required.Thus, when D=1, Q=0, Q+=1 J,K = 1,xD=0, Q=0, Q+=0 J,K = 0,xD=1, Q=1, Q+=1 J,K = x,0D=0, Q=1, Q+=0 J,K = x,1.D-FFJKQDCLK
19 Example 2: D J-K Excitation Table for D should work like a J-K Q Q+ D0 0 1 1 J K Q Q+QJDLogicKCLKJKQTT for J-K1Function isJ-K FF/LatchQDQKJCLK
20 • A counter is a special case of an FSM that cycles through its states (C) Counter Design• A counter is a special case of an FSM that cycles through its stateson receiving triggering clock pluses.• It does not have any external data I/Ps.100No external I/PsResetEACounter O/P000011LogicDNext Statebits001BC010FFsnnCLK• The states need to be encoded by binary bits.
21 State Transition Diagram and Table for a 3-bit Binary Up-Counter Synthesis (3-Bit Up Counter)ResetOutputNext StateToggle Flip-FlopInputsInputPresent StateC B A C+ B+ A+ TC TB TA(a) State TransitionDiagram(b) State Transition Table(What next statewill be given thecurrent state.)FF Excitation Table RevisitedQ Q+ R S J K T Dx xxxx xExcitation table for R-S, J-K, T, and D Flip-Flops
22 From excitation table for FF inputs, get K-map for the FF inputs. CBCBAA11TA=1TC=ABCBAK-maps for Up-Counter Using ToggleFlip-Flops.1TB=AObtain logic expr. for FF I/Ps (as functions of current state bits A,B, C, --- A=QA, B=QB, C=QC) and realize the counter
23 Implementation Using J-K FFs: Counters with More Complex Sequencing (Non-Consecutive Binary Outputs)Present StateNext State011C B A C+ B+ A+x x xx x xx x xState TransitionDiagramImplementation Using J-K FFs:State Transition TablePresentStateNextStateRemapped NextStateC B A C+ B+ A+ JC KC JB KB JA KAx x xx x x x x x x x xx x xx x xx x x x x x x x xx x xx x xx x x x x x x x xQ Q+ J Kxxx 1x 0J-K Flip-Flop Excitation TableState Transition Table and Remapped Next-State Functions
24 Next State Functions x x 1 x 0 0 x x x x x 0 x 1 x x 1 x x x x 0 1 x CBCBAAx x xx x x 0x xx x xJCKC11CBCBAA1 x x xx x x 1x xx x xJBKB11CBCBAAxx x x xx x x xx x 1JAKA11Remapped K-Maps for J-K Implementation.
25 Actual Implementation ( Using J-K) +CABJAJ QCLKK QJ QCLKK QJ QCLKK QAKBCCountsignalABJAKBCJ-K Flip-Flop Implementation of 3 Bit Counter.