Presentation on theme: "1 EECS 465: Digital Systems Lecture Notes # 7 (A) Introduction to Sequential Circuits (B) Latches and Flip-Flops (C) Counter Design SHANTANU DUTT Department."— Presentation transcript:
1 EECS 465: Digital Systems Lecture Notes # 7 (A) Introduction to Sequential Circuits (B) Latches and Flip-Flops (C) Counter Design SHANTANU DUTT Department of Electrical and Computer Engineering University of Illinois, Chicago Phone: (312) : URL:
2 (A) Introduction to Sequential Circuits Current o/p depends on the current i/p and past history of all i/ps seen by the circuit. Where the relevant past history should be representable by a finite number of classes or states No Red Red Light State Reset Encode as state=0 Light = Red O/P = 0 Light = Green O/P = 1 Light = Not green O/P = 0 Light = Not red O/P = 0 Encode as state = 1 State Transition Diagram Design Problem: Output of the circuit is 1 only if it has seen a red light in the past and currently light is green.
3 Circuit-Level Model of a Sequential Circuit. Combinational Circuit Memory Unit Z0Z0 Z m-1 Going to external world x0x0 x n-1 I/p from external point State bits of seq. ckt. Current State Next State yk -1 y0y0 y ’ k-1 y’0y’0
4 Components to store bits ( latches or flip flops ) 1) Problem: can’t store new data Cascade of inverter 0 I/P 1/0O/P A LD Will conduct when A=1, and open when A=0 2) (B) Latches and Flip-Flops
5 Another storage element: 3) Cross coupled NOR gates ( R-S latch ) R=0 0 Q 1 S=1 0 Q R Q S (Set) (Reset) NOR gates ( R-S latch ) Property of a NOR gate A=0 B When one I/P of NOR is 0, it acts like an inverter. When one I/P is 1, then O/P=0. Different I/P conditions for R-S latch: i) R=S=0, current I/P is stored indefinitely ( becomes cascade of inverters) Hold
6 ii) R=1, S=0, when we want to store a 0 in the R-S latch. Q=0, iii) R=0, S=1, when we want to store a 1 in the latch. Q=1, iv) R=1, S=1; Forbidden inputs! Both Q = 0, : Q and its complement have the same value ! Will play havoc in the rest of the logic circuit. Transit to: R=0, S=0. R=1, S=1, both Q and and 0. 0 O/P oscillates. Q R=1 0 S=1 101 0101 0 Oscillates between 1 and 0 when we transit from R=S=1 to R=S=0.
7 Cross-coupled NOR R Q S Cross-coupled NAND R S Q Hold State R=S=0 Hold State R=S=1 Q R=1, S=1 R=0, S=0 Forbidden I/Ps From R, S = 1, 1 transit to R=0, S=1 then Q, transit to 1, 0 ( correctly ) From R, S = 1, 1 transit to R=1, S=0 then Q, correctly transit to 0, 1 Two implementations for R-S latch:
8 4) The D-Latch R-S Latch D S R R1R1 S1S1 Q enb Clocked Latch (level-sensitive clock latch) — see terminology defined later. D=1, S=1, R=0 Q=1, D=0, S=0, R=1 Q=0, enb=0 R 1,S 1 =0 (hold state) enb=1
9 5) The J-K Latch: — Proposed to get rid of the forbidden I/P problem of R-S i) J=1, K=0: (a) Let Q=1, R=0,S=0 Hold state of R-S Q=1, ii) J=0, K=1 Q=0, using a similar analysis iii) J=K=0 Hold state iv) J=K=1, suppose Q=1, =0 R=1, S=0 Q=0, =1 S=1, R=0 Q=1, =0 This type of toggling continues as long as J=K=1, and the latch is enabled ( CLK=1 below ) (b) Let Q=0,, R=0, S=1 Q=1, R R-S Q S R Q 1 0101 0101 1010 1010 CLK K J
10 Latch classification with respect to response to “control signal” Terminology: Note that the terminology below applies to all types of latches: R-S, D, J-K, T, etc., though the examples are given for the R-S latch. i) Transparent Latch: O/P responds to latch I/Ps without any enable or clock signal. R Q S Clock: Fixed frequency alternating 1 and 0 signal ii) Clocked or Level-Sensitive Latch: Q S Clock or enb R O/P responds to I/Ps only when enb or clock is at a pre-determined level (high or low — In this example, it is High) R S Q Symbol: R S Q CLK (high enable) Symbol: or R S Q CLK (low enable)
11 iii) Edge-Triggered Flip-Flop (FF) or simply Flip-Flop O/P will respond to I/Ps only at either: (a) the positive or rising edge of the enb/clock signal (positive edge-triggered FF), or (b) the negative or falling edge of the enb/clock signal (negative edge-triggered FF). Clock: O/P response period for a positive edge-triggered FF. O/P response period for a negative edge-triggered FF O/P response period for a HIGH-enable/clock level-sensitive latch O/P resp. period for a low-enable/clock level sensitive latch Symbol: R S Q CLK Symbol: R S Q CLK
12 Setup Times and Hold Time of FFs and Latches Assume, positive edge-triggered D-FF T Hold relates to propagation delay of another part of circuit. D CLK T Setup relates to propagation delays of various gates in the FF. The high point of the CLK determines the positive edge’s arrival. If negative edge-triggered CLK D T Hold T Setup Negative edge arrival If D-Latch is high-level sensitive: T setup and T hold have to be around the negative edge of clock (more specifically, when the clock begins to go low), similar to negative edge-triggered. If D-Latch is low-level sensitive: T setup and T hold have to be around the positive edge of clock, similar to positive edge-triggered.
13 Solutions to Race Condition Problem with Level Sensitive Latches Solution 1: Master-Slave FF: Master-Slave J-K is a solution to race-condition problem: Any change in Q, during CLK=0 is not propagated to P, and hence back to Q, during the same CLK=0. Any change to Q, will occur in next CLK=0 period. J K Q (O/P responds when CLK goes From 1 to 0) J-K M-S Master-Slave J-K works similar to a J-K latch: E.g. Let J=1, K=1, CLK=1 Q=1, =0 =1, P=0 When CLK=0 Q=0, =1 Q R-S Latch CLK K J Q R S R-S QmQm R S QsQs P Master R-S is level sensitive. Slave R-S is level sensitive.
14 Solution 2: Edge-Triggered FF: Q R S D Clk=1 0 0 Holds D when clock goes low Holds when clock goes low Q =D R S D Clk=0 D Assume D=1 D=1=S Q=1, CLK Q R S D Clk=0 D 0 0 Q responds to internal S signal; responds to internal R signal. When CLK is 1 D I/P is internally sampled but does not appear at the O/P. O/P is held (changing D does not cause any change in internal signals in the FF or in its output) O/P appears (Q=D) D D
15 Characteristic Equations of Latches/FFs The next O/P Q + defined in terms of the current O/P Q and the I/P. (FF/Latch is the simplest possible sequential ckt.) 1) R-S Latch— Truth Table: S(t) R(t) Q(t) Q + = Q( t+ ) x x Values at time t Hold Reset Set Forbidden Q(t)\SR x x 1 Q + = S+ Q (Characteristic equation)
16 Similarly: Characteristic Equations of 2) J-K, Q + = Q + J. 3) D-FF, Q + = D 4) Toggle FF/Latch Q + = T + Q or T-FF / Latch Whenever I/P T is high, the FF will toggle, i.e., Q + =. When T=0, Q + =Q. Of course, these characteristic equations come into play only when the FF/Latch is enabled. Q T Symbol:
17 Excitation Table — Reversed Truth Table — What the inputs to FFs should be for given output transitions (Q Q + ) Q Q + R S J K T D 0 0 x 0 0 x x x x x 0 0 1
18 — Conversion between FFs Example: J-K to D D-FF D 0 1 x Q D x 1 0 D Q O/P function = J J=D Function = K K= Map the D,Q input combination to a Q Q + transition and then map this to J-K excitation required. Thus, when D=1, Q=0, Q + =1 J,K = 1,x D=0, Q=0, Q + =0 J,K = 0,x D=1, Q=1, Q + =1 J,K = x,0 D=0, Q=1, Q + =0 J,K = x,1. This should behave like a D-FF. J K Q D CLK Logic J K Q D CLK
19 Example 2: D J-K Excitation Table for D Q Q + D 0 1 1 J K Q Q Q D J K CLK TT for J-K JK Q Function is Q D CLK J K Q J-K FF/Latch Logic should work like a J-K
20 (C) Counter Design A counter is a special case of an FSM that cycles through its states on receiving triggering clock pluses. It does not have any external data I/Ps. A B C D EReset FFs Logic Counter O/P Next State bits n n CLK The states need to be encoded by binary bits. No external I/Ps
21 Synthesis (3-Bit Up Counter) Reset (a) State Transition Diagram C B A C + B + A + TC TB TA Input Present State Output Next State Toggle Flip-Flop Inputs (b) State Transition Table FF Excitation Table Revisited Q Q + R S J K T D 0 0 x 0 0 x x x x x Excitation table for R-S, J-K, T, and D Flip-Flops (What next state will be given the current state.) State Transition Diagram and Table for a 3-bit Binary Up-Counter
22 From excitation table for FF inputs, get K-map for the FF inputs CB A TA= A CB TC=AB A CB TB=A K-maps for Up-Counter Using Toggle Flip-Flops. Obtain logic expr. for FF I/Ps (as functions of current state bits A, B, C, --- A=Q A, B=Q B, C=Q C ) and realize the counter
23 Counters with More Complex Sequencing (Non-Consecutive Binary Outputs) State Transition Diagram C B A C + B + A x x x x x x x x x Present State Next State State Transition Table Implementation Using J-K FFs: C B A C + B + A + JC KC JB KB JA KA x 1 x 0 x x x x x x x x x x x x 0 1 x x x 1 x x x x x x x x x x x 0 1 x x x 1 x 1 0 x x x x x x x x x x Present State Next State Remapped Next State State Transition Table and Remapped Next-State Functions Q Q + J K x x 1 0 x x 0 J-K Flip-Flop Excitation Table
24 Next State Functions 0 0 x x x 1 x x CB A JCJC x x 1 x x x x 0 CB A KCKC 1 x x x x x x 1 CB A JBJB x 0 1 x x 1 x x CB A KBKB x x x CB A JAJA x x x 0 x CB A KAKA Remapped K-Maps for J-K Implementation.
25 Actual Implementation ( Using J-K) J Q CLK K Q J Q CLK K Q J Q CLK K Q + Count signal A C KBKB BJAJA C A JAJA B KBKB A C J-K Flip-Flop Implementation of 3 Bit Counter.