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Mapping for Better Than Worst-Case Delays In LUT-Based FPGA Designs Kirill Minkovich and Jason Cong VLSI CAD Lab Computer Science Department University of California, Los Angeles Supported by the National Science Foundation under grant CCF

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Variation and its effects Environmental Variation Causes: overheating and voltage fluctuations Addressed (in part) by: cooling and better power supplies Process Variation Causes: dopant density, edge geometry, stress during manufacturing, and much more Addressed (in part) by: Adding a slack of as much as 3-sigma for delay variation Data Variation Causes: output stabilization varying greatly between different data Addressed by: Highly restrictive asynchronous designs and the Razor architecture Solutions Speed Binning and more accurate estimates Only deals with process variation Only deals with process variation Variable Clocking (Razor Architecture) Deals with all 3 variations! Deals with all 3 variations! Intra-die variations in ILD thickness

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High performance circuits Worst-case delay minimization Hitting a wall due to feature size limits Can’t keep up with Moore’s law Can’t keep up with Moore’s law Conservative timing due to variation Conservative timing due to variation Typical case delay minimization Defined: Delay for expected data to propagate through circuit Usually much smaller than worst-case delay Usually much smaller than worst-case delay Harder to optimize circuits Change thinking about circuit optimization Change thinking about circuit optimization Requires special architecture, like the Razor Architecture (MICRO ’03) UCLA VLSICAD LAB3

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Razor flip-flop implementation Error comparator RAZOR FF Main Flip-Flop clk clk_del Shadow Latch Q Logic Stage L1 Logic Stage L2 Error_L 0 1 D Slide borrow from Razor (MICRO ’03) presentation Main flip-flop Clocked faster than worst-case delay Shadow Latch Clocked with delayed clock to catches any errors Error Occurs when main flip-flop and shadow latch differ Next clock cycle, the Shadow latch value moves into the Main Flip-Flop 4

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Razor timing error detection Second sample of logic value used to validate earlier sample Key design issues: Maintaining forward progress Short path impact on shadow-latch Overhead of error detection and correction Main FF Shadow Latch Main FF clk clk_del MEM Slide borrow from Razor (MICRO ’03) presentation

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Razor (output) registers Razor (state) registers Razor (input) registers FSM to Razor transformation Possible to convert most circuits to Razor Stallable buffer State registers Combinational logic Output registers Razor (stabilization) registers Input registers FSM combinational logic Data Data Valid Data Ready Razor Blackbox 6

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Problem formulation Definitions Maximum depth Shadow latch (worst-case delay) Shadow latch (worst-case delay) Target depth Main (overclocked) flip-flip Main (overclocked) flip-flip Performance Measuring Can’t use the clock due to errors! Errors due to overclocking (any switching between target depth and max depth) So we have to use Expected Delay instead of Delay ExpDelay(using target depth d ) = d (Pr(NO error | using clock d)) ExpDelay(using target depth d ) = d (Pr(NO error | using clock d)) + ( d + time recover ) (Pr(error | using clock d)) + ( d + time recover ) (Pr(error | using clock d)) Find d Linear search! Linear search! BestExpDelay = min(ExpDelay( d ) | max_depth/2 ≤ d < max_depth) BestExpDelay = min(ExpDelay( d ) | max_depth/2 ≤ d < max_depth) UCLA VLSICAD LAB7

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Optimization goals The expected delay Total delay for data to propagate and recovery from any errors Reduce probability of an error Reduce probability of an error Straight forward, if we are given a target depth Minimize probability of switching after target depth Minimize probability of switching after target depth What can we do without the target depth? We try to get the switching to occur as early as possible Extra area overhead Hard to compare solutions (special cost function is needed) Clock Switching Activity UCLA VLSICAD LAB8

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BTWMap algorithm overview Decompose into 2-input gates Simulate 256 random input values over all cuts Assign cost based on switching and depth Choose cuts to minimize cost Save the scaled simulation data for next iteration Cut Selection times Area Recovery Target clock assignment Area/performance tradeoff Done!

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UCLA VLSICAD LAB Cut selection Cut ranking Can’t look at just switching activity for each depth For example, cut 2 is better than cut 1 Expired simulation data Keep the old data Assume previous iteration’s costs after still valid but scale them down Allows the algorithm to converge on a solution Keeping the old data, decreases Pr(error) by an average of 3.5% Keeping the old data, decreases Pr(error) by an average of 3.5% Huge improvement since for us Pr(error) <= 5% Huge improvement since for us Pr(error) <= 5% Depth Probability of switching Cut 1Cut 2 33%4% 250%5% 170% 10

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UCLA VLSICAD LAB BTWMap - area recovery (target depth) Idea Find a target depth How much to overclock How much to overclock Ignore the switching the happens below this depth Implementation Set outputs’ target depth Select cuts PO->PI while propagating the target depth Works similar to worst case depth but calculated Works similar to worst case depth but calculated PO->PI using MIN instead PI->PO using MAX Benefits Moderate reduction in area Target depth

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UCLA VLSICAD LAB BTWMap – area-performance tradeoff Idea Relax the minimum switching cost of each gate Give area recovery techniques room to work Implementation Set outputs to the initial amount they can be relaxed Make a relaxation and propagate what your inputs can change using: Depth of the inputs Depth of the inputs How much switching slack is left How much switching slack is left Input to output switching correlation Input to output switching correlation u For example, Pr(y switching|x 1 switched)=75% while Pr(y switching|x 2 switched)=50% while Pr(y switching|x 2 switched)=50% Benefits Accurate relaxation estimates Large reduction in area 12

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BTWMap results example BTWMap mapping comparison Test circuit is PDC from the MCNC benchmark suit Comparing 4 methods A. Depth optimal mapping with depth relaxation on non-critical paths for area saving B. Depth optimal mapping without depth relaxation C. BTWMap D. BTWMap with area recovery. 13

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UCLA VLSICAD LAB What circuits can’t be optimized Maximum Razor clock = (max depth)/2 Already good = switching < 2% at maximum Razor clock Very low switching at maximum Razor clock 4 of the MCNC suite Too bad = switching > 90% at max depth All the switching happens at the very last depth. Very hard to optimize. Have to reduce the switching activity a minimum of 20x at that depth 5 of the MCNC suite Easy to test and exclude Map using ABC and checking switching probabilities 14

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UCLA VLSICAD LAB Sample results The example below is for the MCNC benchmark SEQ ABC BTWMap BTWMap+area ABC BTWMap BTWMap+area Area 1000Area1258Area1111 Max Depth Depth Switch. Prob. Prob. Error Expected Delay Depth Switch. Prob. Prob. Error Expected Delay Depth Switch. Prob. Prob. Error Expected Delay Ave Delay 5.09 Best Pipeline Delay 6.00 Ave Delay3.80 Best Pipeline Delay 5.23 Ave Delay4.28 Best Pipeline Delay

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Results – expected delay and area Performance improvement: 13% with BTWMap and 11% after area recovery The area recovery saves over 16% of the lost area In the best case (ignoring switching), we’re still 3% away from ABC Trading 7% for much better switching activity Expected DelayRatioAreaIncrease CircuitABCBTWMap BTWMap +area BTWMap BTWMap +area ABCBTWMap BTWMap +area BTWMap BTWMap +area alu %92% %8% apex %97% %7% apex % %6% clma %95% %21% misex % %10% pdc %85% %12% s % %11% s % %11% s %84% %7% seq %88% %11% spla %92% %13% Geomean 87.0%88.8% 26.4%10.1% 16

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UCLA VLSICAD LAB Conclusion BTWMap work includes: Methodologies for measuring performance on circuits optimized for average case delay. Algorithms for optimizing circuits for average case delay. Implementation and release these tools (alpha version) Results Summary BTWMap (and the area recovery version) 14% (and 8%) average delay reduction 14% (and 8%) average delay reduction 13% (and 11%) pipeline improvement 13% (and 11%) pipeline improvement 26% (and 10%) area increase 26% (and 10%) area increase 17

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UCLA VLSICAD LAB18

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