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EECS 150 - Components and Design Techniques for Digital Systems Lec 22 – Sequential Logic - Advanced David Culler Electrical Engineering and Computer Sciences.

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Presentation on theme: "EECS 150 - Components and Design Techniques for Digital Systems Lec 22 – Sequential Logic - Advanced David Culler Electrical Engineering and Computer Sciences."— Presentation transcript:

1 EECS 150 - Components and Design Techniques for Digital Systems Lec 22 – Sequential Logic - Advanced David Culler Electrical Engineering and Computer Sciences University of California, Berkeley

2 Traversing Digital Design EE 40 CS61C EECS150 wks 1-6 EECS150 wks 6 - 15 Sequential Circuit Design and Timing


4 Types of Latches We have focused on D-flips –D latch => D FlipFlop => Registers (ld, clr) –Most commonly used today (CMOS, FPGA) Many other types of latches –RS, JK, T –Should be familiar with these too Opportunity to look much more closely at timing behavior Latch vs Flip Flops Timing Methodology

5 Recall: Forms of Sequential Logic Asynchronous sequential logic – “state” changes occur whenever state inputs change (elements may be simple wires or delay elements) Synchronous sequential logic – state changes occur in lock step across all storage elements (using a periodic waveform - the clock) Clock

6 Example – ring oscillator A B CD E X (b) Timing waveform

7 Recall: General Model of Synchronous Circuit Our methodology so far: –registers as D flipflops with common control –Single-phase clock, edge triggered design Assumptions underlying the clean abstraction –Input to FF valid a setup time before clock edge –Outputs don’t change too quickly after clock edge (hold time) »Clk-to-Q => hold time input clock T su ThTh

8 X1 X2 Xn switching network Z1 Z2 Zn Circuits with Feedback How to control feedback? –What stops values from cycling around endlessly

9 "remember" "load" "data" "stored value" "0" "1" "stored value" Simplest Circuits with Feedback Two inverters form a static memory cell –Will hold value as long as it has power applied How to get a new value into the memory cell? –Selectively break feedback path –Load new value into cell

10 Latches Level-sensitive latch –holds value when clock is low –Transparent when clock is high What does it take to build a consistent timing methodology with only latches? –Very hard! All stages transparent at same time. –Require that minimum propagation delay is greater than high phase of the clock (duty period) DQ DQDQ a in clk b a b

11 period duty cycle (in this case, 50%) Clocks Used to keep time –Wait long enough for inputs (R' and S') to settle –Then allow to have effect on value stored Clocks are regular periodic signals –Period (time between ticks) –Duty-cycle (time clock is high between ticks - expressed as % of period)

12 Two-phase non-overlapping clocks Sequential elements partition into two classes phase0 ele’ts feed phase1 phase1 ele’ts feed phase0 Approximate single phase: each register replaced by a pair of latches on two phases Can push logic across (retiming) Can always slow down the clocks to meet all timing constraints DQDQ a in clk0 b a b clk-0 clk1 c/l clk1

13 Master-Slave Structure Construct D flipflop from two D latches clk clk’ clk clk’ clk clk’

14 Latches vs FlipFlips Level sensitive vs edge triggered Very different design methodologies for correct use Both are clocked, but latch is asynchronous –Output can change while clock is high D Clk Q Q FF Latch

15 R S Q Q' R S Q R' S' QQ Q' S' R' Asynchronous R-S Latch Cross-coupled NOR gates –Similar to inverter pair, with capability to force output to 0 (reset=1) or 1 (set=1) Cross-coupled NAND gates –Similar to inverter pair, with capability to force output to 0 (reset=0) or 1 (set=0) 0 1 0 1

16 State Behavior of R-S latch Transition Table Sequential (output depends on history when inputs R=0, S=0) but asynchronous R S Q Q' S(t)R(t)Q(t)Q(t+  ) 0000 0011 0100 0110 1001 1011 110X 111X hold reset set not allowed characteristic equation Q(t+  ) = S + R’ Q(t) 0 00100010 X1X1X1X1 Q(t) R S

17 Theoretical R-S Latch Behavior State Diagram –States: possible values –Transitions: changes based on inputs Q Q' 0 1 Q Q' 1 0 Q Q' 0 0 Q Q' 1 1 SR=00 SR=11 SR=00 SR=10 SR=01 SR=00 SR=10 SR=00 SR=01 SR=11 SR=10 SR=01 SR=10 SR=11 possible oscillation between states 00 and 11 R S Q Q'

18 Reset Hold Set Reset Race R S Q \Q 100 Timing Behavior R S Q Q'

19 Observed R-S Latch Behavior Very difficult to observe R-S latch in the 1-1 state –One of R or S usually changes first Ambiguously returns to state 0-1 or 1-0 –A so-called "race condition" –Or non-deterministic transition SR=00 Q Q' 0 1 Q Q' 1 0 Q Q' 0 0 SR=10 SR=01 SR=00 SR=10 SR=00 SR=01 SR=11 SR=01SR=10 SR=11

20 R S Q Q' Q(t+  ) R S Q(t) SRQ(t)Q(t+  ) 0000 0011 0100 0110 1001 1011 110X 111X hold reset set not allowed characteristic equation Q(t+  ) = S + R’ Q(t) R-S Latch Analysis Break feedback path 0 00100010 X1X1X1X1 Q(t) R S

21 enable' S' Q' Q R' R S Gated R-S Latch Control when R and S inputs matter –Otherwise, the slightest glitch on R or S while enable is low could cause change in value stored –Ensure R & S stable before utilized (to avoid transient R=1, S=1) Set Reset S' R' enable' Q Q' 100

22 clock R' and S' changingstablechangingstable Towards a Synchronous Design Controlling an R-S latch with a clock –Can't let R and S change while clock is active (allowing R and S to pass) –Only have half of clock period for signal changes to propagate –Signals must be stable for the other half of clock period clock' S' Q' Q R' R S

23 clock R SQ Q'R SQ R S Cascading Latches Connect output of one latch to input of another How to stop changes from racing through chain? –Need to control flow of data from one latch to the next –Advance from one latch per clock period –Worry about logic between latches (arrows) that is too fast »Shortest paths, not critical paths

24 Announcements Guest Lecture, Nov 29, Dr. Robert Iannucci, CTO Nokia Sarah Lecture on Testing Methodology Thurs. HW out tonight, due before Break Lab lecture covers “final point” Wireless CP this week Next week TAs will do extended office hours M-W rather than formal lab. Final Check off week 14 No Class Dec 6. Final report Friday Dec. 7. Sign up for 10 min slots –5 min presentation, 5 min Q&A –Arrive 20 mins before scheduled slot to set up

25 Master-Slave Structure Break flow by alternating clocks (like an air-lock) –Use positive clock to latch inputs into one R-S latch –Use negative clock to change outputs with another R-S latch View pair as one basic unit –master-slave flip-flop –twice as much logic –output changes a few gate delays after the falling edge of clock but does not affect any cascaded flip-flops master stage slave stage P P' CLK R SQ Q'R SQ R S CLK CLK’

26 Set 1s catch S R CLK P P' Q Q' Reset Master Outputs Slave Outputs The 1s Catching Problem In first R-S stage of master-slave FF –0-1-0 glitch on R or S while clock is high "caught" by master stage –Leads to constraints on logic (feeding the latch) to be hazard- free master stage slave stage P P' CLK R SQ Q'R SQ R S

27 10 gates D Flip-Flop Make S and R complements of each other in Master stage –Eliminates 1s catching problem »Input only needs to settle by clock edge –Can't just hold previous value (must have new value ready every clock period) –Value of D just before clock goes low is what is stored in flip- flop –Can make R-S flip-flop by adding logic to make D = S + R' Q D Q Q' master stage slave stage P P' CLK R SQ Q'R SQ

28 JK Flip Flops J(t)K(t)Q(t)Q(t+  ) 0000 0011 0100 0110 1001 1011 1101 1110 hold reset set toggle R-S master/slave K J S R Q Q’ Q

29 Q D Clk=1 R S 0 D’ 0 D Q’ negative edge-triggered D flip-flop (D-FF) 4-5 gate delays must respect setup and hold time constraints to successfully capture input characteristic equation Q(t+1) = D holds D' when clock goes low holds D when clock goes low (neg) Edge-Triggered Flip-Flops More efficient solution: only 6 gates –sensitive to inputs only near edge of clock signal (not while high)

30 Q D Clk=1 R S D D’ D Edge-Triggered Flip-Flops (cont’d) D = 0, Clk High 0 1 0 0 0 0 1 1 Hold state Act as inverters

31 0 Q D Clk=1 R S D D’ D Edge-Triggered Flip-Flops (cont’d) D = 1, Clk High 0 1 0 0 0  1 0 1 1 0 1  0

32 D-FF Behavior when CLK=1 Q D Clk=1 R S Dl D’ Du’ D’ DuDu Q’ 0 0->1 D clk D’ Du 0->1 1->0 R=Du’ S=Dl Q Q’ 1->0 0 Change in D propagate through lower and upper latch, but R=S=0, isolating slave

33 Behavior when CLK 1->0 Q D Clk=1 R S Dl D’ Du’ D’ DuDu Q’ 0 1 D clk D’ Du 1 0 R=Du’ S=Dl Q Q’ 0 Falling edge allows latched D to propagate to output latch 1->0 0->1 Q’->0 Q->1

34 D-FF; behavior when CLK==0 Lower output 0 Upper latch retains old D RS unchanged when clock is low data is held Q new D Clk=0 R S D D’ D new D  old D Q’ D’->0 R’=Q=old D 0 D->~D’=D

35 positive edge-triggered FF negative edge-triggered FF D CLK Qpos Qpos' Qneg Qneg' 100 Edge-Triggered Flip-Flops (cont’d) Positive edge-triggered –Inputs sampled on rising edge; outputs change after rising edge Negative edge-triggered flip-flops –Inputs sampled on falling edge; outputs change after falling edge

36 Timing Methodologies Rules for interconnecting components and clocks –Guarantee proper operation of system when strictly followed Approach depends on building blocks used for memory elements –Focus on systems with edge-triggered flip-flops »Found in programmable logic devices –Many custom integrated circuits focus on level-sensitive latches Basic rules for correct timing: –(1) Correct inputs, with respect to time, are provided to the flip-flops –(2) No flip-flop changes state more than once per clocking event

37 there is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized clock data changingstable input clock T su ThTh clock data DQDQ Timing Methodologies (cont’d) Definition of terms –clock: periodic event, causes state of memory element to change; can be rising or falling edge, or high or low level –setup time: minimum time before the clocking event by which the input must be stable (Tsu) –hold time: minimum time after the clocking event until which the input must remain stable (Th)

38 TypeWhen inputs are sampledWhen output is valid unclockedalwayspropagation delay from input change latch level-sensitiveclock highpropagation delay from input change latch(Tsu/Th around fallingor clock edge (whichever is later) edge of clock) master-slaveclock highpropagation delay from falling edge flip-flop(Tsu/Th around fallingof clock edge of clock) negativeclock hi-to-lo transitionpropagation delay from falling edge edge-triggered(Tsu/Th around fallingof clock flip-flopedge of clock) Comparison of Latches and Flip- Flops (cont’d)

39 all measurements are made from the clocking event that is, the rising edge of the clock Typical Timing Specifications Positive edge-triggered D flip-flop –Setup and hold times –Minimum clock width –Propagation delays (low to high, high to low, max and typical) Th 5ns Tw 25ns Tplh 25ns 13ns Tphl 40ns 25ns Tsu 20ns D CLK Q Tsu 20ns Th 5ns

40 IN Q0 Q1 CLK 100 Cascading Edge-triggered Flip-Flops Shift register –New value goes into first stage –While previous value of first stage goes into second stage –Consider setup/hold/propagation delays (prop must be > hold) CLK IN Q0Q1 DQDQOUT

41 timing constraints guarantee proper operation of cascaded components assumes infinitely fast distribution of the clock Cascading Edge-triggered Flip-Flops (cont’d) Why this works –Propagation delays exceed hold times –Clock width constraint exceeds setup time –This guarantees following stage will latch current value before it changes to new value T su 4ns T p 3ns T h 2ns In Q0 Q1 CLK T su 4ns T p 3ns T h 2ns

42 original state: IN = 0, Q0 = 1, Q1 = 1 due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1 CLK1 is a delayed version of CLK0 In Q0 Q1 CLK0 CLK1 100 Clock Skew The problem –Correct behavior assumes next state of all storage elements determined by all storage elements at the same time –This is difficult in high-performance systems because time for clock to arrive at flip-flop is comparable to delays through logic –Effect of skew on cascaded flip-flops: Need Propagation – Skew > Hold Time

43 Summary of Latches and Flip-Flops Development of D-FF –Level-sensitive used in custom integrated circuits »can be made with 4 pairs of gates »Usually follows multiphase non-overlapping clock discipline –Edge-triggered used in programmable logic devices –Good choice for data storage register Historically J-K FF was popular but now never used –Similar to R-S but with 1-1 being used to toggle output (complement state) –Good in days of TTL/SSI (more complex input function: D = JQ' + K'Q –Not a good choice for PALs/PLAs as it requires 2 inputs –Can always be implemented using D-FF Preset and clear inputs are highly desirable on flip-flops –Used at start-up or to reset system to a known state

44 Flip-Flop Features Reset (set state to 0) – R –Synchronous: Dnew = R' Dold (when next clock edge arrives) –Asynchronous: doesn't wait for clock, quick but dangerous Preset or set (set state to 1) – S (or sometimes P) –Synchronous: Dnew = Dold + S (when next clock edge arrives) –Asynchronous: doesn't wait for clock, quick but dangerous Both reset and preset –Dnew = R' Dold + S (set-dominant) –Dnew = R' Dold + R'S(reset-dominant) Selective input capability (input enable/load) – LD or EN –Multiplexer at input: Dnew = LD' Q + LD Dold –Load may/may not override reset/set (usually R/S have priority) Complementary outputs – Q and Q'

45 Maintaining the Digital Abstraction (in an analog world) Circuit design with very sharp transitions Noise margin for logical values Carefully Design Storage Elements (SE) –Internal feedback Structured System Design –SE + CL, cycles must cross SE Timing Methodology –All SE advance state together –All inputs stable across state change V out V dd 0 V in V dd DQ

46 Where does this breakdown? Interfacing to the physical world Can’t tell it “not to change near the clock edge” Digital Abstraction

47 Example Problems DQ DQ Q0 Clock Q1 Async Input Clocked Synchronous System In is asynchronous and fans out to D0 and D1 one FF catches the signal, one does not inconsistent state may be reached! In Q0 Q1 CLK DQ DQ Q0 Clock Q1 Async Input DQ Synchronizer

48 Metastability In worst cast, cannot bound time for FF to decide if inputs can change right on the edge –Circuit has a metastable balance point logic 0 logic 1 horrible example

49 Practical Solution Series of synchronizers –each reduces the chance of getting stuck (exponentially) Make P(metastability) < P(device failure) Oversample and then low pass DQ DQ Q0 Clock Q1 Async Input DQ Synchronizer

50 Metastability throughout the ages Buridan, Jean (1300-58), French Scholastic philosopher, who held a theory of determinism, contending that the will must choose the greater good. Born in Bethune, he was educated at the University of Paris, where he studied with the English Scholastic philosopher William of Ocham. After his studies were completed, he was appointed professor of philosophy, and later rector, at the same university. Buridan is traditionally but probably incorrectly associated with a philosophical dilemma of moral choice called "Buridan's ass." In the problem an ass starves to death between two alluring bundles of hay because it does not have the will to decide which one to eat. Didn’t take EECS 150

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