2 Sequential Circuit A digital circuit whose output depends not only on the present combination of input, but also on the history of the circuit.
3 Sequential Circuit Elements Two basic types: –Latch –Flip-flop The difference is the condition under which the stored bit changes.
4 Sequential Circuit Inputs The LATCH is a sequential circuit with two inputs (SET and RESET). SET – an input that makes the device store a logic 1. RESET – an input that makes the device store a logic 0.
5 Sequential Circuit Outputs Two complementary outputs Outputs are always in opposite logic states.
15 Block Diagram File NAND Latch Gate components are called BOR2: –Bubbled-OR, 2-inputs Inputs are labeled nS and nR. Outputs are labeled Q and nQ. –In Quartus, the n prefix takes the place of the logic inversion bar.
17 Practical Synthesis of the NAND Latch Quartus II does not synthesize the LATCH exactly as shown in Figure 8.15 on the previous slide. Quartus II analyzes the Boolean equation of the original LATCH and reformats the circuit to fit the target device.
20 Switch Bounce The condition where the closure of a switch contact results in a mechanical bounce before the final contact is made. In logic circuits, switch bounce causes several pulses when a switch is closed. –Can cause circuit to behave unpredictably.
24 Gated SR Latch The time when a latch is allowed to change state is regulated. Change of state is regulated by a control signal called ENABLE. Circuit is a NAND latch controlled by steering gates.
26 Latch ENABLE Input Used in two principal ways: –As an ON/OFF signal –As a synchronizing signal
27 ENSRQ t+1 Function 100QtQt No change 1010 1 Reset 1101 0 Set 1111 1 Forbidden 0XXQtQt Inhibited Gated SR Latch Function Table
28 Gated D or Transparent Latch A latch whose output follows its data input when its ENABLE input is active. When ENABLE is inactive, the latch stores the data that was present when ENABLE was last active.
34 VHDL Process Statement PROCESS statement is concurrent. Statements inside the PROCESS are sequential.
35 VHDL – D Latch – 1 -- d_latch_vhdl.vhd -- D latch with active-HIGH level-sensitive enable ENTITY d_latch_vhdl IS PORT( d, ena: IN BIT; q: OUT BIT); END d_latch_vhdl;
36 VHDL – D Latch – 2 ARCHITECTURE a OF d_latch_vhdl IS BEGIN PROCESS ( d, ena) BEGIN IF ( ena = ‘1’) THEN q <= d; END IF; END PROCESS; END a;
37 Instantiating a Latch Primitive Primitive is contained in the Altera library, in a package called maxplus2. Component declaration in maxplus2 package. Unnecessary to declare it in the file used.
38 VHDL – Latch Primitive – 1 -- latch_primitive.vhd -- D latch with active-HIGH level-sensitive enable LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY altera; USE altera.maxplus2.ALL;
39 VHDL – Latch Primitive – 2 ENTITY latch_primitive IS PORT( d_in, enable: INSTD_LOGIC; q_out: OUTSTD_LOGIC); END latch_primitive;
40 VHDL – Latch Primitive – 3 ARCHITECTURE a OF latch_primitive IS BEGIN -- Instantiate a latch from a QUARTUS II primitive latch_primitive: latch PORT MAP (d => d_in, ena => enable, q => q_out); END a;
41 Multibit Latches in VHDL VHDL can be used to implement latches with multiple D inputs and Q outputs and a common ENABLE line. –Use behavioral description with STD_LOGIC_VECTOR types. –Use primitives – predefined components. –Use component from Library of Parameterized Modules (LPM).
42 VHDL – Latch LPM Component – 1 -- latch4_behavioral.vhd -- D latch with active-HIGH level-sensitive enable -- uses a latch component from the -- Library of Parameterized Modules (LPM) LIBRARY ieee; USE ieee.std_logic_1164.ALL; --required for STD_LOGIC types LIBRARY lpm; USE lpm.lpm_components.ALL; -- Required for LPM components
44 VHDL – Latch LPM Component – 3 ARCHITECTURE a OF latch4_lpm IS BEGIN -- instantiate latch from an LPM component latch4 : lpm_latch GENERIC MAP (LPM_WIDTH => 4) PORT MAP ( data => d_in, gate => enable, q => q_out); END a;
46 Flip-Flop Definition A gated latch with a clock input. The sequential circuit output changes when its CLOCK input detects an edge. Edge-sensitive instead of level- sensitive.
47 CLOCK Definitions Positive edge: –The transition from logic ‘0’ to logic ‘1’ Negative edge: –The transition from logic ‘1’ to logic ‘0’ Symbol is a triangle on the CLK (clock) input of a flip-flop.
54 Latch/Flip-Flop Behavior The LATCH transfers data from the data inputs to Q on either a HIGH or LOW voltage level at the ENABLE input. The FLIP-FLOP transfers data from the data inputs to Q on either the POSITIVE (rising), or NEGATIVE (falling) edge of the clock.
64 Synchronous Versus Asynchronous Circuits Synchronous circuits have sequential elements whose outputs change at the same time. Asynchronous circuits have sequential elements whose outputs change at different times.
67 Disadvantages of Asynchronous Circuits Difficult to analyze operations. Intermediate states that are not part of the desired design may be generated.
68 Synchronous and Asynchronous Inputs Synchronous inputs of a flip-flop only affect the output on the active clock edge. Asynchronous inputs of a flip-flop change the output immediately. Asynchronous inputs override synchronous inputs.
69 Flip-Flop Asynchronous Inputs Preset: –An asynchronous set function, usually designated as Clear: –An asynchronous reset function, usually designated as Both Preset and Clear usually have LOW input active levels.
71 CLKJKQ t+1 Function 01XXX10PRESET 10XXX01Clear 00XXX11Forbidden 11Flip-Flop Operates Synchronously JK Flip-Flop Asynchronous Inputs Function Table
72 JK Flip-Flop Asynchronous Inputs Function Table
73 Unused Preset and Clear Inputs Disable by connecting to a logic HIGH (for active-LOW inputs). In Quartus II the asynchronous inputs of all flip-flop primitives are set to a default level of HIGH.
74 Master Reset An asynchronous input used to set a sequential circuit to a known initial state. Usually a RESET tied to the inputs of all flip-flops. When activated, the output of the sequential circuit goes LOW.
81 Flip-Flops in PLDs Flip-flops are usually found in PLDs as registered outputs. A registered output of a PLD is defined as an output having a flip-flop (usually D-type) that stores the output state.
82 Generic Array Logic (GAL) GAL: –A PLD whose outputs can be configured as combinational or registered Programming matrix is designed with electrically erasable logic cells.
83 Generic Array Logic – Macrocell I/O circuit that can be configured as a registered output, a combinational output, or a dedicated input as required. Outputs can also be specified as active- HIGH or active-LOW.
87 MAX 7000S CPLD – 1 Max 7000 CPLD family of devices is manufactured by Altera. EPM7128SLC84-7 is one of two devices installed on the UP-1 and UP-2 Boards. The device is in-circuit programmable.
88 MAX 7000S CPLD – 2 Constructed of a series of Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA). Each LAB has 16 macrocells with similar I/O and programming capability to a low-density PLD. Refer to Figure 8.87 of the text.
89 EPM7128SLC84-7 EPM7Max 7000 FAMILY 128Number of macrocells SIn-system programmable 8484-pin PLCC package 7Speed grade
90 FunctionPins V CC 8 Ground8 JTAG port4 GCLK11 OE11 GCLRn1 GCLK2/OE21 User I/Os60 Total pins84 EPM7128SLC84-7 Pin Summary
91 FLEX 10K CPLD – 1 Volatile: –Does not retain stored information after the power has been removed PLD based on look-up table architecture (LUT). A number of storage elements are used to synthesize logic functions by storing each function as a truth table.