Presentation on theme: "Electronic memory & logic devices. Solid State Physics N N P P +- Transistors And diodes Logic gates Memory devices : Flip flops Flip Flop Flip Flop Flip."— Presentation transcript:
Electronic memory & logic devices
Solid State Physics N N P P +- Transistors And diodes Logic gates Memory devices : Flip flops Flip Flop Flip Flop Flip Flop Output Clock Input Output’ Input 2
Abstract Transistors have six salient features. First, they rapidly switch between two states in response to an input signal. Second, a small input voltage can control a large output voltage. Third, voltage is the common I/O signal carrier. Fourth, wires are the common interconnect. Fifth, common I/O and wires enable addressable signals, which means specific connections between devices. Sixth, amplification and addressable signals enables restoration, because the output voltage greatly exceeds the voltage necessary to control a downstream transistor.
In the schematic below, current through the load resistor determine the output (state) of the device.
Current through the load is determined by the current through the two lower terminals of the device.
The current through the two lower terminals of the device is non-linearly responsive to the input voltage.
Therefore the output voltage is non-linearly responsive to the input voltage.
Abstract Transistors can be assembled into devices that render Boolean logic functions. The input and output voltages represent logic 0 or 1. NAND is the universal logic gate, and underpins design of higher level memory devices like latches and flip-flops.
R A NAND gate If either input is a logic 0, output is a logic 1.
R Function No current travels through circuit if either transistor switch is open (logic 0 input A or B). Thus, no voltage drop across the load (4.7K) resistor and all voltage drop across transistors. Because output is taken across the transistors, rather than the load, and because voltage drop across transistors is high, logic 1 is output if either input A or B is a logic 0.
Vb = 0.6V NAND is the universal logic gate
Abstract NAND gate latch, implemented in flip-flops, is a simple memory device that will latch onto an output state when both inputs are one. If zero is input, the latch output is 1, independent of prior state. The latch will hold state if both inputs are equal to 1.
S QR S QR Prior state = 1 0 Prior state = 0 Holds state if both inputs are one
Abstract D-flip flop implements a NAND gate latch. The flip-flop output equals the Input, if enabled. The enable can be a clock. In this case, the output tracks the input when the clock is a logic 1.
In Q, output Latch Enable 0 or 1 Enable 0 or 1 D-type flip-flop
D QE Latch Output equals input if enabled.
Clock A clock can serve as the enable.
In Output Latch Clock In Output Enable Output tracks input when clock is logic 1.
Abstract JK flip-flops also implement latches. Because of feedback, this flip-flop architecture will toggle output states when both inputs are logic 1. The enable can be a clock. In this case, the state of the flip-flop will toggle at the positive going transition of the clock, if both input are logic 1. Flip-flops have at least four salient features that admit well to implementation in systems. They perform fast computation. They have a consistent definition for logic 0 and 1. They perform the same function independent of their position (context) within a circuit. They have common interconnect and I/O signal carrier, which enable programming via specific device connections.
K QE Input Latch Enable No Change Input 2 J Toggle 1 JK Fli-flop : Output state toggles if both inputs are logic 1. Output Output ’
K QE 1 11 Toggle Latch J Prior output = 1 New output = 0
K QE 1 11 Toggle 0 1 J Prior output = 0 New output = 1 Latch 1 1
A clock can serve as the enable. Each positive going clock transition serves as a trigger. Clock
“Trigger” “Inputs” Bit State Output state toggles if both inputs are logic 1.
“Trigger” “Inputs” Bit State But both flip-flop inputs must be high.
Flip Flop Flip Flop Output Clock Input Output’ Input 2 Output Clock Input 2 Input 1 High Function