Presentation on theme: "DEPARTMENT OF ELECTRONICS AND COMMUNICATION"— Presentation transcript:
1 DEPARTMENT OF ELECTRONICS AND COMMUNICATION MICROPROCESSORS AND MICROCONTROLLERSByR.HARINIDEPARTMENT OF ELECTRONICS AND COMMUNICATION
2 AIMTo have an in depth knowledge of the architecture and programming of 8-bit and 16-bit Microprocessors, Microcontrollers and to study how to interface various peripheral devices with them.
3 OBJECTIVETo study the architecture and Instruction set of 8085 and 8086To develop assembly language programs in 8085 and 8086.To design and understand multiprocessor configurationsTo study different peripheral devices and their interfacing to 8085/8086.To study the architecture and programming of 8051 microcontroller.
4 UNIT I THE 8085 AND 8086 MICROPROCESSORS 8085 Microprocessor architecture-Addressing modes- Instruction set-Programming the 8085UNIT II SOFTWARE ASPECTSIntel 8086 microprocessor - Architecture - Signals- Instruction Set-Addressing Modes-Assembler Directives- Assembly Language Programming-Procedures-Macros-Interrupts And Interrupt Service Routines-BIOS function calls.UNIT III MULTIPROCESSOR CONFIGURATIONS Coprocessor Configuration – Closely Coupled Configuration – Loosely Coupled Configuration –8087 Numeric Data Processor – Data Types – Architecture –8089 I/O Processor –Architecture –Communication between CPU and IOP.UNIT IV I/O INTERFACING Memory interfacing and I/O interfacing with 8085 – parallel communication interface – serial communication interface – timer-keyboard/display controller – interrupt controller – DMA controller (8237) – applications – stepper motor – temperature control.UNIT V MICROCONTROLLERS Architecture of 8051 Microcontroller – signals – I/O ports – memory – counters and timers – serial data I/O – interrupts-Interfacing -keyboard, LCD,ADC & DAC
5 THE 8085 MICROPROCESSOR UNIT I 1.1 Introduction to 8085 1.2 Microprocessor architecture1.3 Instruction set1.4 Addressing modes1.5 Programming the 8085.
6 PROCESSORThe first microprocessor was introduced in 1970 by Intel (named 4004).It ran at the speed of 108KHz.Four years later, Intel created the 8080 running at just over 2 Mhz.This microprocessor was used on the world's firs personal computer, named Altair.Also at this time, IBM started researching for their microprocessor, called POWER (Performance Optimization With Enhanced RISC).
10 1.3 INSTRUCTION SET BASED ON FUNCTIONS Data Transfer Instructions Arithmetic InstructionsLogical InstructionsBranch InstructionsMachine ControlBASED ON LENGTHOne-word or 1-byte instructionsTwo-word or 2-byte instructionsThree-word or 3-byte instructions
11 8085 Instruction SetThe 8085 instructions can be classified as follows:Data transfer operationsBetween RegistersBetween Memory location and a RegistersDirect write to a Register/MemoryBetween I/O device and AccumulatorArithmetic operations (ADD, SUB, INR, DCR)Logic operationsBranching operations (JMP, CALL, RET)
16 1.5 ADDRESSING MODES Implied Addressing: The addressing mode of certain instructions is implied by the instruction’s function. For example, the STC (set carry flag) instruction deals only with the carry flag, the DAA (decimal adjust accumulator) instruction deals with the accumulator.Register Addressing:Quite a large set of instructions call for register addressing. With these instructions, specify one of the registers A through E, H or L as well as the operation code. With these instructions, the accumulator is implied as a second operand. For example, the instruction CMP E may be interpreted as 'compare the contents of the E register with the contents of the accumulator.Most of the instructions that use register addressing deal with 8-bit values. However, a few of these instructions deal with 16-bit register pairs. For example, the PCHL instruction exchanges the contents of the program counter with the contents of the H and L registers.Immediate Addressing:Instructions that use immediate addressing have data assembled as a part of the instruction itself. For example, the instruction CPI 'C' may be interpreted as ‘compare the contents of the accumulator with the letter C. When assembled, this instruction has the hexadecimal value FE43. Hexadecimal 43 is the internal representation for the letter C. When this instruction is executed, the processor fetches the first instruction byte and determines that it must fetch one more byte. The processor fetches the next byte into one of its internal registers and then performs the compare operation.
17 ADDRESSING MODES CONTD… Direct Addressing:Jump instructions include a 16-bit address as part of the instruction. For example, the instruction JMP 1000H causes a jump to the hexadecimal address 1000 by replacing the current contents of the program counter with the new value 1000H. Instructions that include a direct address require three bytes of storage: one for the instruction code, and two for the 16-bit address Register Indirect Addressing:Register indirect instructions reference memory via a register pair. Thus, the instruction MOV M,C moves the contents of the C register into the memory address stored in the H and L register pair. The instruction LDAX B loads the accumulator with the byte of data specified by the address in the B and C register pair.
18 UNIT- II Intel 8086 microprocessor Architecture Signals Instruction setAddressing modesAssembler directivesAssembly language programmingProceduresMacrosInterrupts and interrupt service routines.BIOS Function Calls
20 8086 FEATURES 16-bit Arithmetic Logic Unit 16-bit data bus (8088 has 8-bit data bus)20-bit address bus = 1,048,576 = 1 megThe address refers to a byte in memory.In the 8088, these bytes come in on the 8-bit data bus. In the 8086, bytes at even addresses come in on the low half of the data bus (bits 0-7) and bytes at odd addresses come in on the upper half of the data bus (bits 8-15).The 8086 can read a 16-bit word at an even address in one operation and at anodd address in two operations. The 8088 needs two operations in either case.The least significant byte of a word on an 8086 family microprocessor is at thelower address.
22 8086 ARCHITECTUREThe 8086 has two parts,the Bus Interface Unit (BIU) andthe Execution Unit (EU).The BIU fetches instructions, reads and writes data, and computes the 20-bit address.The EU decodes and executes the instructions using the 16-bit ALU.The BIU contains the following registers:IP - the Instruction PointerCS - the Code Segment RegisterDS - the Data Segment RegisterSS - the Stack Segment RegisterES - the Extra Segment RegisterThe BIU fetches instructions using the CS and IP, written CS:IP, to contractthe 20-bit address. Data is fetched using a segment register (usually the DS)and an effective address (EA) computed by the EU depending on theaddressing mode.
24 PROGRAM MODEL BIU registers (20 bit adder) EU registers ES 8086 Programmer’s ModelESExtra SegmentBIU registers(20 bit adder)CSCode SegmentSSStack SegmentDSData SegmentIPInstruction PointerEU registersAXAHALAccumulatorBXBHBLBase RegisterCXCHCLCount RegisterDXDHDLData RegisterSPStack PointerBPBase PointerSISource Index RegisterDIDestination Index RegisterFLAGS
25 8086/88 internal registers 16 bits (2 bytes each) AX, BX, CX and DX are twobytes wide and each byte canbe accessed separatelyThese registers are used asmemory pointers.Flags will be discussed laterSegment registers are usedas base address for a segmentin the 1 M byte of memory
26 The 8086/8088 Microprocessors: Registers Registers are in the CPU and are referred to by specific namesData registersHold data for an operation to be performedThere are 4 data registers (AX, BX, CX, DX)Address registersHold the address of an instruction or data elementSegment registers (CS, DS, ES, SS)Pointer registers (SP, BP, IP)Index registers (SI, DI)Status registerKeeps the current status of the processorOn an IBM PC the status register is called the FLAGS registerIn total there are fourteen 16-bit registers in an 8086/8088
27 Data Registers: AX, BX, CX, DX Instructions execute faster if the data is in a registerAX, BX, CX, DX are the data registersLow and High bytes of the data registers can be accessed separatelyAH, BH, CH, DH are the high bytesAL, BL, CL, and DL are the low bytesData Registers are general purpose registers but they also perform special functionsAXAccumulator RegisterPreferred register to use in arithmetic, logic and data transfer instructions because it generates the shortest Machine Language CodeMust be used in multiplication and division operationsMust also be used in I/O operations
28 BX CX DX Base Register Also serves as an address register Used in array operationsUsed in Table Lookup operations (XLAT)CXCount registerUsed as a loop counterUsed in shift and rotate operationsDXData registerUsed in multiplication and divisionAlso used in I/O operations
29 Pointer and Index Registers Contain the offset addresses of memory locationsCan also be used in arithmetic and other operationsSP: Stack pointerUsed with SS to access the stack segmentBP: Base PointerPrimarily used to access data on the stackCan be used to access data in other segmentsSI: Source Index registeris required for some string operationsWhen string operations are performed, the SI register points to memory locations in the data segment which is addressed by the DS register. Thus, SI is associated with the DS in string operations.
30 DI: Destination Index register is also required for some string operations.When string operations are performed, the DI register points to memory locations in the data segment which is addressed by the ES register. Thus, DI is associated with the ES in string operations.The SI and the DI registers may also be used to access data stored in arrays
31 Segment Registers - CS, DS, SS and ES Are Address registersStore the memory addresses of instructions and dataMemory OrganizationEach byte in memory has a 20 bit address starting with 0 to or 1 meg of addressable memoryAddresses are expressed as 5 hex digits from FFFFFProblem: But 20 bit addresses are TOO BIG to fit in 16 bit registers!Solution: Memory SegmentBlock of 64K (65,536) consecutive memory bytesA segment number is a 16 bit numberSegment numbers range from 0000 to FFFFWithin a segment, a particular memory location is specified with an offsetAn offset also ranges from 0000 to FFFF
33 Segmented MemorySegmented memory addressing: absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offsetone segmentlinear addresses
34 Memory Address Generation IntelMemory Address GenerationThe BIU has a dedicated adder for determining physical memory addressesOffset Value (16 bits)Segment Register (16 bits)AdderPhysical Address (20 Bits)
35 Example Address Calculation IntelExample Address CalculationIf the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data?29Offset:Segment:Address:
36 SEGMENT:OFFSET ADDRESS Logical Address is specified as segment:offsetPhysical address is obtained by shifting the segment address 4 bits to the left and adding the offset addressThus the physical address of the logical address A4FB:4872 isA4FB0+ 4872A9822
38 The physical address is also called the absolute address. THE CODE SEGMENT0HMemory+CS:IP0400H0056H4000H4056H0400005604056HThe offset is the distance in bytes from the start of the segment.The offset is given by the IP for the Code Segment.Instructions are always fetched with using the CS register.The physical address is also called the absolute address.CS:IP = 400:56Logical AddressSegment RegisterOffsetPhysical orAbsolute Address0FFFFFH
39 0H 0FFFFFH Memory Segment Register Offset Physical Address + DS: EA THE DATA SEGMENTMemorySegment RegisterOffsetPhysical Address+DS:EA05C0005005C00H05C50HDS:EA0H0FFFFFHData is usually fetched with respect to the DS register.The effective address (EA) is the offset.The EA depends on the addressing mode.
40 The stack grows toward decreasing memory locations. THE STACK SEGMENTMemory+SS:SP0A0001000A000H0A100HThe stack is always referenced with respect to the stack segment register.The stack grows toward decreasing memory locations.The SP points to the last or top item on the stack.PUSH - pre-decrement the SPPOP - post-increment the SPThe offset is given by the SP register.SS:SP0H0FFFFFHSegment RegisterOffsetPhysical Address
41 FlagsCarry flagOverflowParity flagDirectionInterrupt enableAuxiliary flagTrapZeroSign6 are status flags3 are control flag
42 Flag RegisterConditional flags:They are set according to some results of arithmetic operation. You do not need to alter the value yourself.Control flags:Used to control some operations of the MPU. These flags are to be set by you in order to achieve some specific purposes.FlagODITSZAPCBit no.151413121110987654321CF (carry) Contains carry from leftmost bit following arithmetic, also contains last bit from a shift or rotate operation.
43 Flag RegisterOF (overflow) Indicates overflow of the leftmost bit during arithmetic.DF (direction) Indicates left or right for moving or comparing string data.IF (interrupt) Indicates whether external interrupts are being processed or ignored.TF (trap) Permits operation of the processor in single step mode.
44 SF (sign) Contains the resulting sign of an arithmetic operation (1=negative) ZF (zero) Indicates when the result of arithmetic or a comparison is zero. (1=yes)AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized arithmetic.PF (parity) Indicates the number of 1 bits that result from an operation.
45 Macros avoid repetitious SAS code create generalizable and flexible SAS codepass information from one part of a SAS job to anotherconditionally execute data steps and PROCsdynamically create code at execution time
47 Procedures Initial call to run an external program Run a LCA model to simulate dataEstimate a model of simulated dataCollect necessary outputCheck if output read is indeed output wantedCollect output in a single data matrix
48 Instruction Set Mov destination, source add, inc, dec and sub instructionsInput/OutputString InstructionsMachine ControlFlag Manipulation.
50 Interrupts &Interrupt Service Routine An interrupt signals the processor to suspend its current activity(i.e. running your program) and to pass control to an interrupt service program (i.e. part of the operating system).A software interrupt is one generated by a program (as opposed toone generated by hardware).The 8086 int instruction generates a software interrupt.It uses a single operand which is a number indicating which MSDOSsubprogram is to be invoked.This subprogram handles a variety of I/O operations by callingappropriate subprograms.
51 MAXIMUM MODE Maximum mode Maximum mode is designed to be used with a coprocessor exists in the system.All the control signals (except RD) are not generated by the microprocessor.But we still need those control signals.Solution:8288.
52 8086 maximum & minimum modes The mode is controlled by MN/MX.Maximum mode is obtained by connecting MN/MX to low and minimum mode is by connecting it to high.Having two different modes (minimum and maximum) is used only 8088/8086.Each mode enables a different control structure.Minimum mode operation and control signals are very similar to those of 8085.So bit peripherals can be used with 8086 without special considerations.Easy and least expensive way to build single processor systems
56 UNIT III Coprocessor Configuration Closely Coupled Configuration Loosely Coupled Configuration8087 Numeric Data Processor-architectureData types8089 I/O Processor-ArchitectureCommunication between CPU and IOP
60 Control Unit Status Register Control unit: To synchronize the operation of the coprocessor and the processor.This unit has a Control word and Status word and Data BufferIf instruction is an ESCape (coprocessor) instruction, the coprocessor executes it, if notthe microprocessor executes.Status register reflects the over all operation of the coprocessor.Status Register
61 Status Register C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summaryPE Precision errorUE Under flow errorOE Overflow errorZE Zero errorDE Denormalized errorIE Invalid errorB Busy bitB-Busy bit indicates that coprocessor is busy executing a task. Busy can be tested by examining the status or by using the FWAIT instruction.C3-C0 Condition code bits indicates conditions about the coprocessor.TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack.ES-Error summary bit is set if any unmasked error bit (PE, UE, OE, ZE, DE, or IE) is set. In the 8087 the error summary is also caused a coprocessor interrupt.PE- Precision error indicates that the result or operand executes selected precision.UE-Under flow error indicates the result is too large to be represent with the current precision selected by the control word.OE-Over flow error indicates a result that is too large to be represented. If this error is masked, the coprocessor generates infinity for an overflow error.ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number.DE-Denormalized error indicates at least one of the operand is denormalized.IE-Invalid error indicates a stack overflow or underflow, indeterminate from (0/0,0,-0,etc) or the use of a NAN as an operand. This flag indicates error such as those producedby taking the square root of a negative number.
62 CONTROL REGISTERControl register selects precision, rounding control, infinity control.It also masks an unmasks the exception bits that correspond to the rightmost Six bits ofstatus register.Instruction FLDCW is used to load the value into the control register.IC Infinity controlRC Rounding controlPC Precision controlPM Precision controlUM Underflow maskOM Overflow maskZM Division by zero maskDM Denormalized operand maskIM Invalid operand mask
63 RC –Rounding control determines the type of rounding. ROUNDING CONTROL IC –Infinity control selects either affine or projective infinity. Affine allows positive and negative infinity, while projective assumes infinity is unsigned.INFINITY CONTROL0 = Projective1 = AffineRC –Rounding control determines the type of rounding.ROUNDING CONTROL00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zeroPC- Precision control sets the precision of he result as define in tablePRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary)Exception Masks – It Determines whether the error indicated by the exception affectsthe error bit in the status register. If a logic1 is placed in one of the exception control bits,corresponding status register bit is masked off.
64 Numeric Execution Unit This performs all operations that access and manipulate the numeric data in thecoprocessor’s registers.Numeric registers in NUE are 80 bits wide.NUE is able to perform arithmetic, logical and transcendental operations as well assupply a small number of mathematical constants from its on-chip ROM.Numeric data is routed into two parts ways a 64 bit mantissa bus anda 16 bit sign/exponent bus.
65 Data TypesInternally, all data operands are converted to the 80-bit temporary real format.We have 3 types.Integer data typePacked BCD data typeReal data typeExampleConverting a decimal number into a Floating-point number.1) Converting the decimal number into binary form.2) Normalize the binary number3) Calculate the biased exponent.4) Store the number in the floating-point format.Step Result1)2) = * 263) =4 ) Sign = 0Exponent =Significand =In step 3 the biased exponent is the exponent a 26 or 110,plus a bias of (7FH)single precision no use 7F and double precision no use 3FFFH.IN step 4 the information found in prior step is combined to form the floating point no.
66 UNIT V Architecture of 8051 Signals Operational features Memory and I/O addressingInterruptsInstruction setApplications.
67 Microcontroller : A single chip A smaller computer On-chip RAM, ROM, I/O ports...Example：Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC 16XCPURAMROMA single chipSerial COM PortI/O PortTimerMicrocontroller
68 Microprocessor vs. Microcontroller CPU is stand-alone, RAM, ROM, I/O, timer are separatedesigner can decide on the amount of ROM, RAM and I/O ports.expansiveversatilitygeneral-purposeMicrocontrollerCPU, RAM, ROM, I/O and timer are all on a single chipfix amount of on-chip ROM, RAM, I/O portsfor applications in which cost, power and space are criticalsingle-purposeversatility 多用途的: any number of applications for PC
69 Block Diagram External interrupts On-chip ROM for program code Timer/CounterInterrupt ControlOn-chip RAMTimer 1Counter InputsTimer 0CPUSerial PortBus Control4 I/O PortsOSCP0 P1 P2 P3TxD RxDAddress/Data
72 Port 0 with Pull-Up Resistors DS500087518951Vcc10 KPort 0
73 Some 8-bitt Registers of the 8051 ABR0R1R3R4R2R5R7R6DPHDPLPCDPTRSome bit RegisterSome 8-bitt Registers of the 8051
74 Stack in the 8051The register used to access the stack is called SP (stack pointer) register.The stack pointer in the 8051 is only 8 bits wide, which means that it can take value 00 to FFH. When 8051 powered up, the SP register contains value 07.7FH30H2FH20H1FH17H10H0FH07H08H18H00HRegister Bank 0(Stack) Register Bank 1Register Bank 2Register Bank 3Bit-Addressable RAMScratch pad RAM
80 MOV Rn, A ;n=0,..,7 ADD A, Rn MOV DPL, R6 MOV DPTR, A MOV Rm, Rn Register Addressing ModeMOV Rn, A ;n=0,..,7ADD A, RnMOV DPL, R6MOV DPTR, AMOV Rm, Rn
81 Direct Addressing Mode Although the entire of 128 bytes of RAM can be accessed using direct addressing mode, it is most often used to access RAM loc. 30 – 7FH.MOV R0, 40HMOV 56H, AMOV A, 4 ; ≡ MOV A, R4MOV 6, 2 ; copy R2 to R6; MOV R6,R2 is invalid !
83 SETB bit ; bit=1 CLR bit ; bit=0 SETB C ; CY=1 SETB P0.0 ;bit 0 from port 0 =1SETB P3.7 ;bit 7 from port 3 =1SETB ACC.2 ;bit 2 from ACCUMULATOR =1SETB 05 ;set high D5 of RAM loc. 20hNote:CLR instruction is as same as SETBi.e.:CLR C ;CY=0But following instruction is only for CLR:CLR A ;A=0
84 DEC byte ;byte=byte-1 INC byte ;byte=byte+1 INC R7 DEC A DEC 40H ; =-1
85 LOOP and JUMP Instructions Conditional Jumps :JZJump if A=0JNZJump if A/=0DJNZDecrement and jump if A/=0CJNE A,byteJump if A/=byteCJNE reg,#dataJump if byte/=#dataJCJump if CY=1JNCJump if CY=0JBJump if bit=1JNBJump if bit=0JBCJump if bit=1 and clear bit
87 UNIT IV Memory Interfacing and I/O interfacing Parallel communication interfaceSerial communication interfaceTimerKeyboard /display controllerInterrupt controllerDMA controllerProgramming and applications
88 Accessing I/O Devices I/O address mapping Memory-mapped I/O Reading and writing are similar to memory read/writeUses same memory read and write signalsMost processors use this I/O mappingIsolated I/OSeparate I/O address spaceSeparate I/O read and write signals are neededPentium supports isolated I/O64 KB address spaceCan be any combination of 8-, 16- and 32-bit I/O portsAlso supports memory-mapped I/O
89 Accessing I/O Devices (cont’d) Accessing I/O ports in PentiumRegister I/O instructionsin accumulator, port8 ; direct formatUseful to access first 256 portsin accumulator,DX ; indirect formatDX gives the port addressBlock I/O instructionsins and outsBoth take no operands---as in string instructionsins: port address in DX, memory address in ES:(E)DIouts: port address in DX, memory address in ES:(E)SIWe can use rep prefix for block transfer of data
90 An Example I/O Device Keyboard Keyboard controller scans and reports Key depressions and releasesSupplies key identity as a scan codeScan code is like a sequence number of the keyKey’s scan code depends on its position on the keyboardNo relation to the ASCII value of the keyInterfaced through an 8-bit parallel I/O portOriginally supported by 8255 programmable peripheral interface chip (PPI)
91 An Example I/O Device (cont’d) 8255 PPI has three 8-bit registersPort A (PA)Port B (PB)Port C (PC)These ports are mapped as follows8255 register Port addressPA (input port) 60HPB (output port) 61HPC (input port) 62HCommand register 63H
92 An Example I/O Device (cont’d) Mapping of 8255 I/O ports
93 An Example I/O Device (cont’d) Mapping I/O ports is similar to mapping memoryPartial mappingFull mappingSee our discussion in Chapter 16Keyboard scan code and status can be read from port 60H7-bit scan code is available fromPA0 – PA6Key status is available from PA7PA7 = 0 – key depressedPA0 = 1 – key released
94 I/O Data Transfer Data transfer involves two phases A data transfer phaseIt can be done either byProgrammed I/ODMAAn end-notification phaseInterruptThree basic techniquesInterrupt-driven I/O (discussed in Chapter 20)
95 I/O Data Transfer (cont’d) Programmed I/ODone by busy-waitingThis process is called pollingExampleReading a key from the keyboard involvesWaiting for PA7 bit to go lowIndicates that a key is pressedReading the key scan codeTranslating it to the ASCII valueWaiting until the key is releasedProgram 19.1 uses this process to read input from the keyboard
96 I/O Data Transfer (cont’d) Direct memory access (DMA)Problems with programmed I/OProcessor wastes time pollingIn our exampleWaiting for a key to be pressed,Waiting for it to be releasedMay not satisfy timing constraints associated with some devicesDisk read or writeDMAFrees the processor of the data transfer responsibility
98 I/O Data Transfer (cont’d) DMA is implemented using a DMA controllerDMA controllerActs as slave to processorReceives instructions from processorExample: Reading from an I/O deviceProcessor gives details to the DMA controllerI/O device numberMain memory buffer addressNumber of bytes to transferDirection of transfer (memory I/O device, or vice versa)
99 I/O Data Transfer (cont’d) Steps in a DMA operationProcessor initiates the DMA controllerGives device number, memory buffer pointer, …Called channel initializationOnce initialized, it is ready for data transferWhen ready, I/O device informs the DMA controllerDMA controller starts the data transfer processObtains bus by going through bus arbitrationPlaces memory address and appropriate control signalsCompletes transfer and releases the busUpdates memory address and count valueIf more to read, loops back to repeat the processNotify the processor when doneTypically uses an interrupt
100 I/O Data Transfer (cont’d) DMA controller details
101 I/O Data Transfer (cont’d) DMA transfer timing
102 I/O Data Transfer (cont’d) 8237 DMA controller
103 I/O Data Transfer (cont’d) 8237 supports four DMA channelsIt has the following internal registersCurrent address registerOne 16-bit register for each channelHolds address for the current DMA transferCurrent word registerKeeps the byte countGenerates terminal count (TC) signal when the count goes from zero to FFFFHCommand registerUsed to program 8257 (type of priority, …)
104 I/O Data Transfer (cont’d) Mode registerEach channel can be programmed toRead or writeAutoincrement or autodecrement the addressAutoinitialize the channelRequest registerFor software-initiated DMAMask registerUsed to disable a specific channelStatus registerTemporary registerUsed for memory-to-memory transfers
105 Interrupt to Processor What is a Timer?A device that uses highspeed clock input to provide a series of time or count-related eventsCounter RegisterSystem Clock0x1206Reload on Zero÷000000Clock DividerCountdown RegisterInterrupt to ProcessorI/O Control
106 Inside the Timer High Byte Low Byte Counter Register GO Register at offsets 0x04, 0x00 (write only)GO Registeroffset 0x08, immediately movesCounter Reg value into Current CounterCurrent Counter(not directly readable by software)Latch Registeroffset 0x0C, write a ``1'' to immediately writeCurrent Counter value to readable Latch RegLatched Counterat offsets 0x04, 0x00 (read only)
107 Setting the Timer's Counter Registers Counter is usually programmed to reach zero X times per secondTo program the timer to reach zero 100 times per secondExample: For a 2 MHz-based timer, 2MHz / 100 = 20,000#define TIMER1 0xint time;time = / 100;timer = (timer_p) TIMER1;timer>countLow = (unsigned char) (time & 0xff);timer>countHigh = (unsigned char) ((time > 8) & 0xff);timer>go = (unsigned char) 0x1;
108 Interrupt vs. Polled I/O Polled I/O requires the CPU to ask a device (e.g. toggle switches) if the device requires servicingFor example, if the toggle switches have changed positionSoftware plans for polling the devices and is written to know when a device will be servicedInterrupt I/O allows the device to interrupt the processor, announcing that the device requires attentionThis allows the CPU to ignore devices unless they request servicing (via interrupts)Software cannot plan for an interrupt because interrupts can happen at any time therefore, software has no idea when an interrupt will occurThis makes it more difficult to write codeProcessors can be programmed to ignore interruptsWe call this masking of interruptsDifferent types of interrupts can be masked (IRQ vs. FIQ)
109 IRQ and FIQ Program Status Register N To disable interrupts, set the corresponding “F” or “I” bit to 1On interrupt, processor switches to FIQ32_mode registers or IRQ32_mode registersOn any interrupt (or) Switch register banksCopy PC and CPSR to R14 and SPSRChange new CPSR mode bitsSWI TrapN…ZCVIFM4M3M2M1M0
115 8251 USART Methods of Data communication a) Simplex b) Duplex c) Half DuplexArchitectureControl WordMode Instruction control wordCommand instruction control word
116 TEXT BOOKSRamesh S.Gaonkar, “Microprocessor - Architecture, Programming and Applications with the 8085”, Penram International publishing private limited, fifth edition.(UNIT-1: – Chapters 3,5,6 and programming examples from chapters 7-10)A.K. Ray & K.M.Bhurchandi, “Advanced Microprocessors and peripherals- Architectures, Programming and Interfacing”, TMH, 2002 reprint. (UNITS 2 to 5: – Chapters 1-6, , 8, 16)
117 REFERENCESDouglas V.Hall, “Microprocessors and Interfacing: Programming and Hardware”, TMH, Third editionYu-cheng Liu, Glenn A.Gibson, “Microcomputer systems: The 8086 / 8088 Family architecture, Programming and Design”, PHI 2003Mohamed Ali Mazidi, Janice Gillispie Mazidi, “The 8051 microcontroller and embedded systems”, Pearson education, 2004.