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Jan-01HERAB-FCS1 Hera-B Fast Control System G. Hochweller G. Delfs P. Gasiorek.

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Presentation on theme: "Jan-01HERAB-FCS1 Hera-B Fast Control System G. Hochweller G. Delfs P. Gasiorek."— Presentation transcript:

1 Jan-01HERAB-FCS1 Hera-B Fast Control System G. Hochweller G. Delfs P. Gasiorek

2 Jan-01HERAB-FCS2 Master Fiber TX Fiber TX Fiber RX Fiber RX Daughter System Overview VME Crate Backplane Optical Fiber Links Twisted Pair (2x30 )

3 Jan-01HERAB-FCS3 front panel signals Master Module VME interface, registers FLT interface FLT inhibit logic event reordering logic event rejection logic fiber data selection SHARC interface statistics, histogram

4 Jan-01HERAB-FCS4 Master Module, Front Panel Signals Input (TTL)Output (NIM) BX-Pulse First Bunch Trigger 1 Trigger 2 Trigger 3 Trigger 4 Handshake FLT Disable FLT-Enable Output (TTL) FLT-Accepted FLT-Rejected Handshake BX-Pulse FLT-Enable FLT-Accepted FLT-Rejected Handshake First Level Trigger Data Connector

5 Jan-01HERAB-FCS5 FEA VME P1 Master Module, VME Interface and Registers FEA VME P2 fifo depth BA + 4 readout duration BA + 8 control bits BA + 16 trigger offset BA + 20 buffer delay BA + 12 VME BUS random factor BA + 24 daughter command BA + 28 VME event (write only) BA + 40 latest accept BA + 0 BA = VME base address (bits ) 8 bits32 bits

6 Jan-01HERAB-FCS6 Master Module, FLT interface FLT connector diff. line receiver diff. line driver FLT_BX latch FLT handshake generation FLT_ACC FLT_BX BX_FLT FLT_ACCEPT FLT_HANDSHAKE

7 Jan-01HERAB-FCS7 Master Module, event reordering logic BXP synchro- nization trigger random trigger FLT event FLT_ACC request arbitration VME trigger BX minus trigger offset FLT_BX reordering RAM (dual port) ADDR DATA ADDR BX minus latest accept RQ code event found 0 1 MPX

8 Jan-01HERAB-FCS8 Master Module, FLT inhibit logic BX FLT_BX B A A - B B A A > B latest accept B A A - B event too late

9 Jan-01HERAB-FCS9 Master Module, event rejection logic readout buffer overflow OR event too fast reject event inhibit FLT (VME) inhibit FLT (LEMO)

10 Jan-01HERAB-FCS10 Master Module, readout buffer overflow handshake (VME) handshake (LEMO) OR readout buffer overflow event found 0 1 MPX handshake mode readout duration counter load decr =0 data readout duration BX pulse B A A = B fifo depth fifo fill counter incr decr

11 Jan-01HERAB-FCS11 Master Module, event too fast event too fast event too fast counter load decr =0 data buffer delay BX pulse event found AND

12 Jan-01HERAB-FCS12 BX cnt BA + 96 BA LD load BX TAG Master Module, statistics and histogram BA = VME base address (bits ) 32 bits 64 bits reset statistics LEMO inhibit cnt BA + 68 CLR total inhibit cnt BA + 64 CLR 'too fast' inhibit cnt BA + 76 CLR VME inhibit cnt BA + 72 CLR FLT latency histo BA BA+2043 'too late' inhibit cnt BA + 84 CLR buffer ovfl inhibit cnt BA + 80 CLR update histo VME data 256*32 bits

13 Jan-01HERAB-FCS13 Master Module, fiber data selection priority arbitration comm high comm low event FLT-BX comm high comm low FLT #, BX # altern. fiber data

14 Jan-01HERAB-FCS14 Master Module, SHARC interface SHARC link FIFO 16 words 84 bits FLT BX (8) physical BX (8) FLT (16) trigger code (4) 96 bits MPX 4 bits eventlink ready BX TAG (48)

15 Jan-01HERAB-FCS15 Fiber Transmitter Module FAN OUT FEA HSSL TX DATA (20) BX pulse (diff) DATA (ser) FAN OUT (8) DATA (ser) FC 266 FC Fiber

16 Jan-01HERAB-FCS16 Fiber Receiver Module FEA HSSL RCV FC Fiber DATA (20) BXP DATA (20) BXP (diff.) DATA (20) BXP (diff.)

17 Jan-01HERAB-FCS17 front panel signals Daughter Module data from master, address decoding, registers event offset BXP, TP delay backplane data generation data selection BXP TP BXP_DEL TP_DEL data (20) register delay correction CAN BUS Interface

18 Jan-01HERAB-FCS18 Daughter Module, Front Panel Signals Input SIG-1 (TTL) SIG-2 (TTL) Cluster/Daughter Address Code Connector Fiber Data Input Connector Diagnostic Connector CAN Bus Connectors

19 Jan-01HERAB-FCS19 addr decod Daughter Module, Data Input and Registers RCV strobe pulse gener trigger mask BXP delay error handling fiber data input conn BXP offset strobe pattern 8 bits3 bits addr code conn (diff.) (23) BXP ERR data (20) CLU (6) DAU (6) test pulse delay test pulse trigger offset TEST-PULSE ERR_128 HIT

20 Jan-01HERAB-FCS20 Daughter Module, address decoding OR B A A = B DAUGHTER (6) AND HIT OR= 0 B A A = B = 0 CLUSTER (6) DAUGHTER (6) CLUSTER (6) from ADDRESS CODE CONNECTOR from FIBER DATA INPUT

21 Jan-01HERAB-FCS21 Daughter Module, BXP and TP delay BXP_DEL* progr delay line * 0.5 ns BXP delay BX pulse BXP_DEL TP_DEL* progr delay line * 0.5 ns TP delay Test pulse TP_DEL

22 Jan-01HERAB-FCS22 Daughter Module, event offset RAM address counter (0...7) BXP event offset RAM (dual port) ADDR DATA ADDR data with offset B A A - B BXP OFFSET (3) data from master

23 Jan-01HERAB-FCS23 Daughter Module, delay correction latch (23) CLK QD latch (23) CLK QD latch (23) CLK QD BXP data with offset corrected data delay < 20 ns delay ns delay > 70 ns

24 Jan-01HERAB-FCS24 Daughter Module, data selection data code select TP request data code (4) BX# count CNT QD LD FLT# count CNT QD LD data (16) (16) (8) FLT RAN VME LE1 LE2 LE3 LE4 TP trigger delay TP AND MASK OR (8) LD FLT# LD BX# FLT# BX# trigger code gener trigger found trigger code backplane data generation

25 Jan-01HERAB-FCS25 Daughter Module, backplane data SWI FLT-ACC (level) FLT-ACC (pulse) latch (39) STROBE (8) FLT_BX# (7) BX# (8) FLT# (16) SIG-1 SIG-2 BXPTP EN_TP backplane


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