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Chapter 4: The Embedded Computing Platform Computer as Components Embedded Systems Laboratory Dept. of Computer Science & Engineering National Sun Yat-Sen.

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Presentation on theme: "Chapter 4: The Embedded Computing Platform Computer as Components Embedded Systems Laboratory Dept. of Computer Science & Engineering National Sun Yat-Sen."— Presentation transcript:

1 Chapter 4: The Embedded Computing Platform Computer as Components Embedded Systems Laboratory Dept. of Computer Science & Engineering National Sun Yat-Sen University Presenter: Chung-Fu Kao

2 4/9/2002 The Embedded Computing System© C.-F. Kao 2 Chapter view CPU bus, I/O devices, and interfacing The CPU system as a framework for understanding design methodology Development environments and debugging An alarm clock design

3 4/9/2002 The Embedded Computing System© C.-F. Kao 3 Typical PC hardware platform CPU CPU bus memory DMA controller timers bus interface bus interface high-speed bus low-speed bus device intr ctrl

4 4/9/2002 The Embedded Computing System© C.-F. Kao 4 Introduction Computer platform  Microprocessors  I/O devices  Memory How to interconnect microprocessors and devices using the CPU bus CPU device keyboard display memory ?

5 4/9/2002 The Embedded Computing System© C.-F. Kao 5 The CPU bus Wire vs. bus  Wire: a 1-bit line between two devices  Bus: a collection of wires with a protocol wire n bus

6 4/9/2002 The Embedded Computing System© C.-F. Kao 6 Action Bus protocol The simplest bus protocol is the four-cycle handshake time enq ack data

7 4/9/2002 The Embedded Computing System© C.-F. Kao 7 Typical bus signals Clock  provides synchronization to the bus components R/W’  true when bus is reading Address  a n1 -bit bundle Data  a n2 -bit bundle Data ready’

8 4/9/2002 The Embedded Computing System© C.-F. Kao 8 A typical microprocessor bus the CPU can read/write devices or memory, bus devices of memory cannot initiate a transfer CPU Device 1 memory clock R/W’ data rdy’ address data

9 4/9/2002 The Embedded Computing System© C.-F. Kao 9 Timing diagrams time A B C zero one rising falling stable changing 10 ns Timing constraint

10 4/9/2002 The Embedded Computing System© C.-F. Kao 10 A simple transfer example

11 4/9/2002 The Embedded Computing System© C.-F. Kao 11 Transfer with ‘wait’ states

12 4/9/2002 The Embedded Computing System© C.-F. Kao 12 State diagrams for the bus read transaction Get data Done Address (start here) See ack Wait CPU Send data Release ack Address (start here) ack Wait Device

13 4/9/2002 The Embedded Computing System© C.-F. Kao 13 Bus read state diagram Get data Done Address (start here) Wait See ack one data send/receive per transfer cycle How to speedup the transfer ?

14 4/9/2002 The Embedded Computing System© C.-F. Kao 14 Burst transfer

15 4/9/2002 The Embedded Computing System© C.-F. Kao 15 Bus architectures: Tri-state design 1-bit tri-state design System tri-state bus enable data_out data_in tri_out ………

16 4/9/2002 The Embedded Computing System© C.-F. Kao 16 Bus architectures: Multiplexing design End of Chapter 4.2.1

17 4/9/2002 The Embedded Computing System© C.-F. Kao 17 I/O techniques Programmed I/O  data are exchanged between CPU and I/O  CPU must wait until the I/O operation is complete Interrupt-driven I/O  CPU can continues to execute other instructions before I/O operation has completed Direct Memory Access (DMA)  CPU does not involve the I/O transfer

18 4/9/2002 The Embedded Computing System© C.-F. Kao 18 DMA: Direct Memory Access The DMA controller includes 3 registers  a starting address register  a length register  a status register Cycle stealing Data count Data register Address register Control Logic DMA REQ INTR DMA ACK Read Write

19 4/9/2002 The Embedded Computing System© C.-F. Kao 19 Possible DMA configuration

20 4/9/2002 The Embedded Computing System© C.-F. Kao 20 Slave BIU Timer Bus example: ARM bus ARM supports an on-chip bus: AMBA  Advanced Microcontroller Bus Architecture Master BIU CPU Master BIU Master N AHB/ASB BUS Decoder Slave BIU On-chip RAM Slave BIU Other APB slaves Arbiter …… Interrupt Controller BIU: Bus Interface Unit APB BUS APB Bridge Slave BIU LED

21 4/9/2002 The Embedded Computing System© C.-F. Kao 21 AMBA features Pipelining  only AHB or ASB Burst transfers  1, 4, 8, 16-beat transfer Split transactions  release the current transfer Multiple bus masters

22 4/9/2002 The Embedded Computing System© C.-F. Kao 22 Bus components devices Slave BIU Timer Master BIU CPU Master BIU Master N AHB/ASB BUS Decoder Slave BIU On-chip RAM Slave BIU Other APB slaves Arbiter …… Interrupt Controller BIU: Bus Interface Unit APB BUS APB Bridge Slave BIU LED

23 4/9/2002 The Embedded Computing System© C.-F. Kao 23 Memory device organization The most basic way to characterize a memory is by its capacity A 4-Mbit memory aspect ratio :  as a 1M x 4-bit array, MAX of 2 20 different addresses  as a 4M x 1-bit array, MAX of 2 22 different addresses

24 4/9/2002 The Embedded Computing System© C.-F. Kao 24 Random-Access Memories (RAMs) There are two major categories of RAM:  static RAM (SRAM)  dynamic RAM (DRAM) The differences between SRAM and DRAM  SRAM is faster than DRAM  SRAM consumes more power than DRAM  more DRAM can be put on a single chip  DRAM values must be periodically refreshed

25 4/9/2002 The Embedded Computing System© C.-F. Kao 25 SRAM SRAM doesn’t need CLOCK signal Block diagram Timing diagram SRAM 32K x 8 address chip select output enable write enable Data_in Data_out CS’ R/W’ Adrs Data From SRAM From CPU

26 4/9/2002 The Embedded Computing System© C.-F. Kao 26 DRAM Single transistor and capacitor per bit CPU address bus is split into a row and a column address NO clock Refreshed  CAS-before-RAS refresh DRAM address chip select output enable write enable Data_in Data_out

27 4/9/2002 The Embedded Computing System© C.-F. Kao 27 Other DRAMs FPM DRAM  fast page mode switch (burst) EDO DRAM  extended data out SDRAM  synchronous DRAM

28 4/9/2002 The Embedded Computing System© C.-F. Kao 28 Read-Only Memories (ROMs) Read only, cannot write any data to ROMs ROMs can store data without any power ROM size  height: n input line, consists 2 n addressable entries  width: the number of bits in each addressable entry A ROM can encode a collection of logic functions directly from the truth table

29 4/9/2002 The Embedded Computing System© C.-F. Kao 29 ROMs Mask ROM Programmable ROM (PROM)  write once Erasable Programmable ROM (EPROM)  can be erased using UV light and then reprogrammed Electrically Erasable Programmable ROM  using high voltages for erasure and reprogramming Flash ROM

30 4/9/2002 The Embedded Computing System© C.-F. Kao 30 I/O devices Timers / counters A/D and D/A converters Keyboards LEDs Displays Touchscreens

31 4/9/2002 The Embedded Computing System© C.-F. Kao 31 Timers and counters Very similar:  a timer is incremented by a periodic signal  a counter is incremented by an asynchronous, occasional signal Rollover causes interrupt

32 4/9/2002 The Embedded Computing System© C.-F. Kao 32 Watchdog timer Watchdog timer is periodically reset by system timer If watchdog is not reset, it generates an interrupt to reset the host (CPU) CPU reset Watchdog Timer time-out

33 4/9/2002 The Embedded Computing System© C.-F. Kao 33 A/D and D/A converters Analog/digital (A/D) or digital/analog (D/A) converters (ADC/DAC) To interface non-digital devices to embedded systems A typical A/D interface has two major digital inputs  a data port  a clock input

34 4/9/2002 The Embedded Computing System© C.-F. Kao 34 DAC

35 4/9/2002 The Embedded Computing System© C.-F. Kao 35 ADC

36 4/9/2002 The Embedded Computing System© C.-F. Kao 36 Keyboards Switch de-bouncing Encoded keyboard  An array of switches is read by an encoder row

37 4/9/2002 The Embedded Computing System© C.-F. Kao 37 LEDs Light-emitting diodes (LEDs) +5 V + Anode (+) Cathode (-)

38 4/9/2002 The Embedded Computing System© C.-F. Kao 38 Displays Common use: 7-segment LCD display Other high-resolution displays  cathode ray tube (CRT)  liquid crystal display (LCD) passive matrix active matrix

39 4/9/2002 The Embedded Computing System© C.-F. Kao 39 Touchscreens Includes input and output device Input device is a two-dimensional voltmeter X

40 4/9/2002 The Embedded Computing System© C.-F. Kao 40 Touchscreen position sensing ADC voltage Push ↓ spacer ball conductive sheets end of chapter 4.5

41 4/9/2002 The Embedded Computing System© C.-F. Kao 41 Design with microprocessors System architecture Hardware design The PC as a platform Debugging Manufacturing testing

42 4/9/2002 The Embedded Computing System© C.-F. Kao 42 System architecture – Hardware Hardware elements  CPU  bus  memory  I/O devices: networking, sensors, etc.

43 4/9/2002 The Embedded Computing System© C.-F. Kao 43 System architecture – Software Functional description must be broken into pieces:  conceptual organization  performance  testability  maintenance Consider the H/W-S/W trade-off  using DMA to move data rather than a programmed loop

44 4/9/2002 The Embedded Computing System© C.-F. Kao 44 Hardware design target system host system serial line Hardware: evaluation board Software:  cross compiler: compiles code on host for target system.  cross debugger: displays target state, allows target system to be controlled.

45 4/9/2002 The Embedded Computing System© C.-F. Kao 45 Evaluation board

46 4/9/2002 The Embedded Computing System© C.-F. Kao 46 The PC as a platform Advantages:  cheap and easy to get  rich and familiar software environment Disadvantages:  requires a lot of hardware resources  not well-adapted to real-time  high power consumption

47 4/9/2002 The Embedded Computing System© C.-F. Kao 47 Typical PC hardware platform CPU CPU bus memory DMA controller timers bus interface bus interface high-speed bus low-speed bus device intr ctrl

48 4/9/2002 The Embedded Computing System© C.-F. Kao 48 Typical busses ISA (Industry Standard Architecture)  original IBM PC bus, low-speed by today’s standard. PCI (Peripheral Component Interconnect)  standard for high-speed interfacing  33 or 66 MHz. USB (Universal Serial Bus), IEEE 1394 (Firewire)  relatively low-cost serial interface with high speed.

49 4/9/2002 The Embedded Computing System© C.-F. Kao 49 Software elements IBM PC uses BIOS (Basic I/O System) to implement low-level functions:  boot-up  minimal device drivers BIOS has become a generic term for the lowest- level system software

50 4/9/2002 The Embedded Computing System© C.-F. Kao 50 Debugging embedded systems Challenges:  target system may be hard to observe  target may be hard to control  may be hard to generate realistic inputs  setup sequence may be complex

51 4/9/2002 The Embedded Computing System© C.-F. Kao 51 Software debuggers A monitor program residing on the target provides basic debugger functions Debugger should have a minimal footprint in memory User program must be careful not to destroy debugger program, but, should be able to recover from some damage caused by user code

52 4/9/2002 The Embedded Computing System© C.-F. Kao 52 Breakpoints A breakpoint allows the user to stop execution, examine system state, and change state Replace the breakpointed instruction with a subroutine call to the monitor program

53 4/9/2002 The Embedded Computing System© C.-F. Kao 53 ARM breakpoints 0x400 MUL r4,r6,r6 0x404 ADD r2,r2,r4 0x408 ADD r0,r0,#1 0x40c B loop uninstrumented code 0x400 MUL r4,r6,r6 0x404 ADD r2,r2,r4 0x408 ADD r0,r0,#1 0x40c BL bkpoint code with breakpoint

54 4/9/2002 The Embedded Computing System© C.-F. Kao 54 Breakpoint handler actions Save registers Allow user to examine machine Before returning, restore system state  safest way to execute the instruction is to replace it and execute in place  put another breakpoint after the replaced breakpoint to allow restoring the original breakpoint (pp )

55 4/9/2002 The Embedded Computing System© C.-F. Kao 55 In-circuit emulators A microprocessor in-circuit emulator is a specially-instrumented microprocessor Allows you to stop execution, examine CPU state, modify registers

56 4/9/2002 The Embedded Computing System© C.-F. Kao 56 Logic analyzers A logic analyzer is an array of low-grade oscilloscopes:

57 4/9/2002 The Embedded Computing System© C.-F. Kao 57 Manufacturing testing Goal: ensure that manufacturing produces defect-free copies of the design Can test by comparing unit being tested to the expected behavior  but running tests is expensive Maximize confidence while minimizing testing cost

58 4/9/2002 The Embedded Computing System© C.-F. Kao 58 Testing concepts Yield: proportion of manufactured systems that work  proper manufacturing maximizes yield  proper testing accurately estimates yield Field return: defective unit that leaves the factory.

59 4/9/2002 The Embedded Computing System© C.-F. Kao 59 Faults Manufacturing problems can be caused by many thing Fault model: model that predicts effects of a particular type of fault Fault coverage: proportion of possible faults found by a set of test  having a fault model allows us to determine fault coverage

60 4/9/2002 The Embedded Computing System© C.-F. Kao 60 Software vs. hardware testing When testing code, we have no fault model  we verify the implementation, not the manufacturing  simple tests work well to verify software manufacturing Hardware requires manufacturing tests in addition to implementation verification

61 4/9/2002 The Embedded Computing System© C.-F. Kao 61 Hardware fault models Stuck-at 0/1 fault model:  output of gate is always 0/1 0010

62 4/9/2002 The Embedded Computing System© C.-F. Kao 62 Combinational testing Every gate can be stuck-at-0, stuck-at-1 Usually test for single stuck-at-faults  one fault at a time  multiple faults can mask each other We can generate a test for a gate by:  controlling the gate’s input  observing the gate’s output through other gates

63 4/9/2002 The Embedded Computing System© C.-F. Kao 63 Sequential testing A state machine is combinational logic + registers Sequential testing is considerably harder  a single stuck-at fault affects the machine on every cycle  fault behavior on one cycle can be masked by same fault on other cycles

64 4/9/2002 The Embedded Computing System© C.-F. Kao 64 Scan chains A scannable register operates in two modes:  normal  scan forms an element in a shift register

65 4/9/2002 The Embedded Computing System© C.-F. Kao 65 Scan chain cell SEL MUX SEL MUX BSRPDR Input pin scan Scan input Shift clock Update clock Scan output EXTEST INTEST Input signal to logic

66 4/9/2002 The Embedded Computing System© C.-F. Kao 66 Boundary scan IEEE Std JTAG boundary scan Serial data in Serial data out System interconnectSerial test interconnect

67 4/9/2002 The Embedded Computing System© C.-F. Kao 67 Embedded ICE


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