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Anuj Kumar - Atrenta Andy Wu - TSMC

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1 Anuj Kumar - Atrenta Andy Wu - TSMC
A Comprehensive Metrics Driven Methodology to Measure and Improve Soft-IP Quality Anuj Kumar - Atrenta Andy Wu - TSMC

2 Background and Motivation
Standardize IP Handoff & Acceptance Quality Checks To define a comprehensive set of quality checks to assess the implementation readiness for soft IPs to enable a smooth IP handoff / acceptance flow. These quality checks are derived from Atrenta’s Reference GuideWare 2.0 Methodology for IP and SoC RTL Signoff and later renamed as “TSMC Soft IP Quality Golden Rules” TSMC Soft IP Quality Checks should be equally applicable for different types of Soft IP e.g. internal, legacy, or 3rd party RTL IPs / Blocks Enable Easy Adoption of the Flow to Benefit a Wide Variety of IP-SoC Ecosystem Partners The IP Qualification flow should be easy to setup Get to the meaningful (high coverage low noise) results with self guided and systematic approach Provide Portable, Easy to Read / Correlate, and Quality Metrics Objective-based Handoff / Acceptance Reports Flow Should be Scalable and Easy to Integrate in Existing Design Flow Environments

3 Overview of TSMC 9000 Soft IP Qualification Program
Online IP Ecosystem Partners End Customers IP1 Atrenta DashBoard IP supplier 1 Chip project 1 IP 2 IP supplier 2 Chip project 2 TSMC IP Kit TSMC IP Kit IP 3 IP supplier 3 Chip project 3 Handoff IP n Inspection / Acceptance Atrenta DataSheet IP supplier n Chip project n

4 TSMC IP Handoff Kit TSMC IP Handoff Kit TSMC IP Handoff Kit
GuideWare goals Doc, training, scripts Lint CDC DFT Power Constr Physical Training module Scripts, setup Quickstart Guide IP Design Intent …. IP reports RTL SDC SGDC UPF/CPF FSDB,… waivers Deliverables Atrenta DataSheet Atrenta DashBoard SpyGlass Clean IP 4

5 TSMC IP Handoff Kit – Inputs / Outputs
Std. Design Constraints Simulation Inputs (SDC, VCD/FSDB, UPF/CPF) Project file SGDC file Waiver file Other setup files Tech Libs (.lib) RTL (.v/.sv/.vhd) TSMC IP Handoff Methodology SpyGlass IP Handoff Deliverables RTL+TechLibs RTL Tech Libs Design Analysis/Quality Metrics Reports CDC Fault Covg Power SDC Coverage DataSheet DashBoard moresimple count Sign_off SpyGlass Setup Files SDC SpyGlass Project File (.prj) UPF/CPF VCD/FSDB/SAIF Waivers (.swl) SGDC

6 Key Soft IP-Kit Quality Checks
Best practices lint checks IP readiness for simulation & synthesis analysis Identification of deadcode, x-assignment, unreachable states Multi mode/corner/design scenarios RTL Power Estimation Power Intent(UPF/CPF) verification Fault/Test Coverage Analysis & Transition) Clock/Reset Propagation (Glitch, convergence) Analysis Asynchronous Clock Domain Crossing Path Verification Timing constraints(SDC) checks for completeness & consistency Verification of Timing Exceptions(FP,MCP) Area, timing(negative slack paths) & congestion analysis TSMC IP Kit SG-Lint SG-AdvanceLint SG-Power SG-PowerVerify SG-DFT SG-Clocks SG-Constraints SG-Txv SG-Physical SpyGlass Clean IP

7 TSMC IP Kit Execution Flow
Design Read >% aipk_read -top foo –srcfile foo.f –libfile lib.f –sdcfile foo.sdc activity_file foo.vcd Design Setup Checks >% aipk_read –top foo Basic Design Checks >% aipk_run –top foo –goals basic_check Advanced Design Checks >% aipk_run –top foo –goals adv_check IP Packaging >% aipk_pack –top foo –save_all Auto-generation of SpyGlass setup files (.prj, .sgdc, .swl, .dat ,etc.) Generation of Design Read DashBoard report Ensures that RTL is read in successfully Identifies unconstrained clock/resets in the design Ensures that design setup is complete & correct Runs basic IP handoff checks (Lint, CDC-Structural, DFT, SDC, Power) Generates quality report for basic design checks/goals Runs advanced IP handoff checks (CDC functional, Lint functional & physical) Generates overall quality report combining results for basic & advanced checks Packages an IP with design intent, setup & analysis reports

8 Soft IP Quality Metrics DashBoard Report
The Atrenta DashBoard is first of the 2 management reports. The DashBoard provides a pass/fail status of the IP/block. For each IP/Block there are 2 sections – Design Objectives and Quality Goals First click – Here we are showing the status of the block for key design objectives like CDC, power, test, etc. – The Value column has the actual results extracted from SpyGlass results for the IP. The ‘success criteria’’ is user defined and captures the desired goal for the IP. Based on the comparison of measured vs. desired, the pass/fail status shows a traffic light pattern of red/yellow/green. Second click – the quality goals section captures the overall quality of the IP/block as measured by different goals defined by the IP kit. These range from lint, clocks, resets, test, power, etc. and for each goal the report captures the number of fatals, errors and warnings. Also captured are any waivers that were applied during the analysis in the interest of transparency. Again user defined success criteria for tolerance to fatals, errors and warnings is used to report the pass/fail status. Additionally each quality goal has a hypertext link to the more detailed SpyGlass report for users to double click on the exact violations reported by the DashBoard.

9 IP Specification/Datasheet Report
TSMC IP Kit generates the SpyGlass DataSheet report capturing key design specifications and profile statistics, once all goals run are finished Design Read Design Setup Check Design Analysis IP Packaging

10 Sample Results from TSMC IP Kit Analysis
IPStats CDC Test SDC Power Gate Count Instance Count Flop Count Unsynchronized CDCs Synchronized CDCs Test Test % ports constrained % registers constrained No. of unverified FP No. of unverified MCP Internal (mW) Leakage (uW) Switching (mW) Core-1  21885  8817  462 130 22 98 94.3 100 4 72.9 2.3 Vendor A 46637 36 212 88 85.3 65 350 79 Vendor B 639021 227585 8907 22027 40626 99 92.3 81 23 2880 15 Vendor C -IP1 57000 23000 2537 275 757 98.7 2 11 13.9 4.9 Vendor C-IP2 95000 39000 9000 4279 1387 91.2 89 40 21.7 Vendor C-IP3 110000 47000 4806 2552 3802 94.1 12 24.2 Vendor D-IP1  489245 94023 47 91.8 118 1870 115 Vendor D-IP2 907303 210201 59125 121 91 117 8140 20 Vendor E-IP1 70439 20125 4546 1300 523 99.7 94.9 8 9.46 64.2 0.95 30+ Soft IPs qualified from 20 different IP vendors enrolled in the TSMC Soft IP 9000 Program so far….

11 TSMC IP Kit – A Typical User Adoption Flow
Legacy IP New RTL blocks 3rd party IP IP Suppliers TSMC IP Kit STANDARDIZED IP INSPECTION Atrenta DataSheet Atrenta DashBoard + IP design intent IP1 IP1 IP1 IP1 IP1 IP1 Legacy IP blocks New RTL blocks 3rd party IP HIGH QUALITY IP BLK 1 BLK 2 SoC Integrators BLK3 BLK n MINIMIZE ITERATIONS SMOOTH SoC INTEGRATION SoC

12 TSMC IP Kit – User Benefits
Standardized inspection flow for all IPs including ones from internal sources (new, legacy, older designs)  Maximize internal IP re-use Propagate IP design intent – SDC/SGDC, waivers, *PF, … for chip integration  IP integrates efficiently Beyond functional verification… Verify IP for CDC, SDC, DFT, *PF, …  Fully verified IP Automated regression flow runs the IP kit nightly and generates DataSheet & DashBoard reports  Automatically track IP updates/ bug fixes Review DataSheet and DashBoard to select the correct IP  IP selection based on objective quality & spec metrics Create an IP repository with published reports  Streamline IP delivery and track usage

13 Summary / Conclusion SpyGlass, TSMC Soft IP Quality Golden/GuideWare Rules and Atrenta Design analysis reports(DashBoard/DataSheet) together provide a comprehensive, detailed and design objective based Soft-IP quality assessment report. TSMC and Atrenta have partnered to adapt these tools for TSMC’s soft IP Qualification Program. A comprehensive set of quality checks, as included in TSMC IP Kit, has been defined and documented in Design Metric Reports. TSMC IP Kit Flow successfully adopted by 20+ IP ecosystem partners, which was quite helpful in improving the implementation readiness for their various Soft-IPs. Summary results of IPs for IP ecosystem partners are posted on TSMC Online

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