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DAC 2014 - IP Track Submission A Comprehensive Metrics Driven Methodology to Measure and Improve Soft-IP Quality Anuj Kumar - Atrenta Andy Wu - TSMC.

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Presentation on theme: "DAC 2014 - IP Track Submission A Comprehensive Metrics Driven Methodology to Measure and Improve Soft-IP Quality Anuj Kumar - Atrenta Andy Wu - TSMC."— Presentation transcript:

1 DAC IP Track Submission A Comprehensive Metrics Driven Methodology to Measure and Improve Soft-IP Quality Anuj Kumar - Atrenta Andy Wu - TSMC

2 2 DAC IP Track Submission Background and Motivation Standardize IP Handoff & Acceptance Quality Checks  To define a comprehensive set of quality checks to assess the implementation readiness for soft IPs to enable a smooth IP handoff / acceptance flow.  These quality checks are derived from Atrenta’s Reference GuideWare 2.0 Methodology for IP and SoC RTL Signoff and later renamed as “TSMC Soft IP Quality Golden Rules”  TSMC Soft IP Quality Checks should be equally applicable for different types of Soft IP e.g. internal, legacy, or 3 rd party RTL IPs / Blocks Enable Easy Adoption of the Flow to Benefit a Wide Variety of IP-SoC Ecosystem Partners  The IP Qualification flow should be easy to setup  Get to the meaningful (high coverage low noise) results with self guided and systematic approach Provide Portable, Easy to Read / Correlate, and Quality Metrics Objective-based Handoff / Acceptance Reports Flow Should be Scalable and Easy to Integrate in Existing Design Flow Environments

3 3 DAC IP Track Submission IP supplier 1 IP supplier 2 IP supplier 3 IP supplier n … TSMC Online TSMC Online IP1 IP 2 IP 3 IP n Chip project 1 Chip project 2 Chip project 3 IP Ecosystem Partners Chip project n … End Customers Handoff TSMC IP Kit Inspection / Acceptance TSMC IP Kit Atrenta DashBoard Atrenta DataSheet Overview of TSMC 9000 Soft IP Qualification Program

4 4 DAC IP Track Submission TSMC IP Handoff Kit IP SpyGlass Clean IP SpyGlass Clean IP IP reports Atrenta DataSheet Atrenta DashBoard IP Design Intent …. IP Design Intent …. RTL waivers GuideWare goals Doc, training, scripts Quickstart Guide Training module Lint CDC DFT Power Constr SDC SGDC SDC SGDC UPF/CPF FSDB,… UPF/CPF FSDB,… Scripts, setup Deliverables Physical TSMC IP Handoff Kit

5 5 DAC IP Track Submission TSMC IP Handoff Kit TSMC IP Handoff Kit – Inputs / Outputs IP Handoff Deliverables TSMC IP Handoff Methodology Design Analysis/Quality Metrics Reports CDC Fault Covg Power SDC Coverage DataSheet DashBoard moresimple count Sign_off RTL+TechLibs RTL Tech Libs SpyGlass Project file SGDC file Waiver file Other setup files Tech Libs (.lib) RTL (.v/.sv/.vhd) Std. Design Constraints Simulation Inputs (SDC, VCD/FSDB, UPF/CPF) SpyGlass Setup Files SDC SpyGlass Project File (.prj) UPF/CPF VCD/FSDB/SAIF Waivers (.swl) SGDC

6 6 DAC IP Track Submission Key Soft IP-Kit Quality Checks  Best practices lint checks  IP readiness for simulation & synthesis analysis  Identification of deadcode, x-assignment, unreachable states  Multi mode/corner/design scenarios RTL Power Estimation  Power Intent(UPF/CPF) verification  Fault/Test Coverage Analysis & Transition)  Clock/Reset Propagation (Glitch, convergence) Analysis  Asynchronous Clock Domain Crossing Path Verification  Timing constraints(SDC) checks for completeness & consistency  Verification of Timing Exceptions(FP,MCP)  Area, timing(negative slack paths) & congestion analysis TSMC IP Kit SG-Power SG-PowerVerify SG-DFT SG-Clocks SG-Txv SG-Constraints SG-Lint SG-Physical IP SpyGlass Clean IP SpyGlass Clean IP SG-AdvanceLint

7 7 DAC IP Track Submission TSMC IP Kit Execution Flow IP Packaging >% aipk_pack –top foo –save_all Advanced Design Checks >% aipk_run –top foo –goals adv_check Basic Design Checks >% aipk_run –top foo –goals basic_check Design Setup Checks >% aipk_read –top foo Design Read >% aipk_read -top foo –srcfile foo.f –libfile lib.f –sdcfile foo.sdc -activity_file foo.vcd Auto-generation of SpyGlass setup files (.prj,.sgdc,.swl,.dat,etc.) Generation of Design Read DashBoard report Ensures that RTL is read in successfully Identifies unconstrained clock/resets in the design Ensures that design setup is complete & correct Runs basic IP handoff checks (Lint, CDC- Structural, DFT, SDC, Power) Generates quality report for basic design checks/goals Runs advanced IP handoff checks (CDC functional, Lint functional & physical) Generates overall quality report combining results for basic & advanced checks Packages an IP with design intent, setup & analysis reports

8 8 DAC IP Track Submission Soft IP Quality Metrics DashBoard Report

9 9 DAC IP Track Submission IP Specification/Datasheet Report TSMC IP Kit generates the SpyGlass DataSheet report capturing key design specifications and profile statistics, once all goals run are finished Design Read Design Setup Check Design Analysis IP Packaging

10 10 DAC IP Track Submission Sample Results from TSMC IP Kit Analysis IPStatsCDCTestSDCPower Gate Count Instance Count Flop Count Unsynchronized CDCs Synchronized CDCs Test % ports constrained % registers constrained No. of unverified FP No. of unverified MCP Internal (mW) Leakage (uW) Switching (mW) Core Vendor A Vendor B Vendor C -IP Vendor C-IP Vendor C-IP Vendor D-IP Vendor D-IP Vendor E-IP … 30+ Soft IPs qualified from 20 different IP vendors enrolled in the TSMC Soft IP 9000 Program so far….

11 11 DAC IP Track Submission TSMC IP Kit – A Typical User Adoption Flow IP1 New RTL blocks New RTL blocks IP1 3 rd party IP IP1 Legacy IP Legacy IP IP1 New RTL blocks New RTL blocks IP1 3 rd party IP IP1 Legacy IP blocks Legacy IP blocks SoC STANDARDIZED IP INSPECTION HIGH QUALITY IP SMOOTH SoC INTEGRATION MINIMIZE ITERATIONS IP Suppliers SoC Integrators BLK 1 BLK 2 BLK3 BLK n TSMC IP Kit Atrenta DataSheet Atrenta DashBoard + IP design intent

12 12 DAC IP Track Submission TSMC IP Kit – User Benefits Beyond functional verification… Verify IP for CDC, SDC, DFT, *PF, …  Fully verified IP Beyond functional verification… Verify IP for CDC, SDC, DFT, *PF, …  Fully verified IP Propagate IP design intent – SDC/SGDC, waivers, *PF, … for chip integration  IP integrates efficiently Propagate IP design intent – SDC/SGDC, waivers, *PF, … for chip integration  IP integrates efficiently Standardized inspection flow for all IPs including ones from internal sources (new, legacy, older designs)  Maximize internal IP re-use Standardized inspection flow for all IPs including ones from internal sources (new, legacy, older designs)  Maximize internal IP re-use Automated regression flow runs the IP kit nightly and generates DataSheet & DashBoard reports  Automatically track IP updates/ bug fixes Automated regression flow runs the IP kit nightly and generates DataSheet & DashBoard reports  Automatically track IP updates/ bug fixes Review DataSheet and DashBoard to select the correct IP  IP selection based on objective quality & spec metrics Review DataSheet and DashBoard to select the correct IP  IP selection based on objective quality & spec metrics Create an IP repository with published reports  Streamline IP delivery and track usage Create an IP repository with published reports  Streamline IP delivery and track usage

13 13 DAC IP Track Submission Summary / Conclusion SpyGlass, TSMC Soft IP Quality Golden/GuideWare Rules and Atrenta Design analysis reports(DashBoard/DataSheet) together provide a comprehensive, detailed and design objective based Soft-IP quality assessment report. TSMC and Atrenta have partnered to adapt these tools for TSMC’s soft IP 9000 Qualification Program. A comprehensive set of quality checks, as included in TSMC IP Kit, has been defined and documented in Design Metric Reports. TSMC IP Kit Flow successfully adopted by 20+ IP ecosystem partners, which was quite helpful in improving the implementation readiness for their various Soft-IPs. Summary results of IPs for IP ecosystem partners are posted on TSMC Online


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