Presentation on theme: "Anuj Kumar - Atrenta Andy Wu - TSMC"— Presentation transcript:
1Anuj Kumar - Atrenta Andy Wu - TSMC A Comprehensive Metrics Driven Methodology to Measure and Improve Soft-IP QualityAnuj Kumar - AtrentaAndy Wu - TSMC
2Background and Motivation Standardize IP Handoff & Acceptance Quality ChecksTo define a comprehensive set of quality checks to assess the implementation readiness for soft IPs to enable a smooth IP handoff / acceptance flow.These quality checks are derived from Atrenta’s Reference GuideWare 2.0 Methodology for IP and SoC RTL Signoff and later renamed as “TSMC Soft IP Quality Golden Rules”TSMC Soft IP Quality Checks should be equally applicable for different types of Soft IP e.g. internal, legacy, or 3rd party RTL IPs / BlocksEnable Easy Adoption of the Flow to Benefit a Wide Variety of IP-SoC Ecosystem PartnersThe IP Qualification flow should be easy to setupGet to the meaningful (high coverage low noise) results with self guided and systematic approachProvide Portable, Easy to Read / Correlate, and Quality Metrics Objective-based Handoff / Acceptance ReportsFlow Should be Scalable and Easy to Integrate in Existing Design Flow Environments
3Overview of TSMC 9000 Soft IP Qualification Program OnlineIP EcosystemPartnersEnd CustomersIP1AtrentaDashBoardIP supplier 1Chip project 1IP 2IP supplier 2Chip project 2TSMC IP KitTSMC IP KitIP 3IP supplier 3Chip project 3HandoffIP n…Inspection /Acceptance…AtrentaDataSheetIP supplier nChip project n
4TSMC IP Handoff Kit TSMC IP Handoff Kit TSMC IP Handoff Kit GuideWare goalsDoc, training, scriptsLintCDCDFTPowerConstrPhysicalTrainingmoduleScripts,setupQuickstartGuideIP Design Intent….IP reportsRTLSDCSGDCUPF/CPFFSDB,…waiversDeliverablesAtrentaDataSheetAtrentaDashBoardSpyGlass CleanIP4
6Key Soft IP-Kit Quality Checks Best practices lint checksIP readiness for simulation & synthesis analysisIdentification of deadcode, x-assignment, unreachable statesMulti mode/corner/design scenarios RTL Power EstimationPower Intent(UPF/CPF) verificationFault/Test Coverage Analysis & Transition)Clock/Reset Propagation (Glitch, convergence) AnalysisAsynchronous Clock Domain Crossing Path VerificationTiming constraints(SDC) checks for completeness & consistencyVerification of Timing Exceptions(FP,MCP)Area, timing(negative slack paths) & congestion analysisTSMC IP KitSG-LintSG-AdvanceLintSG-PowerSG-PowerVerifySG-DFTSG-ClocksSG-ConstraintsSG-TxvSG-PhysicalSpyGlass CleanIP
7TSMC IP Kit Execution Flow Design Read>% aipk_read -top foo –srcfile foo.f –libfile lib.f –sdcfile foo.sdc activity_file foo.vcdDesign Setup Checks>% aipk_read –top fooBasic Design Checks>% aipk_run –top foo –goals basic_checkAdvanced Design Checks>% aipk_run –top foo –goals adv_checkIP Packaging>% aipk_pack –top foo –save_allAuto-generation of SpyGlass setup files(.prj, .sgdc, .swl, .dat ,etc.)Generation of Design Read DashBoard reportEnsures that RTL is read in successfullyIdentifies unconstrained clock/resets in the designEnsures that design setup is complete & correctRuns basic IP handoff checks (Lint, CDC-Structural, DFT, SDC, Power)Generates quality report for basic design checks/goalsRuns advanced IP handoff checks (CDC functional, Lint functional & physical)Generates overall quality report combining results for basic & advanced checksPackages an IP with design intent, setup & analysis reports
8Soft IP Quality Metrics DashBoard Report The Atrenta DashBoard is first of the 2 management reports. The DashBoard provides a pass/fail status of the IP/block.For each IP/Block there are 2 sections – Design Objectives and Quality GoalsFirst click – Here we are showing the status of the block for key design objectives like CDC, power, test, etc. – The Value column has the actual results extracted from SpyGlass results for the IP. The ‘success criteria’’ is user defined and captures the desired goal for the IP. Based on the comparison of measured vs. desired, the pass/fail status shows a traffic light pattern of red/yellow/green.Second click – the quality goals section captures the overall quality of the IP/block as measured by different goals defined by the IP kit. These range from lint, clocks, resets, test, power, etc. and for each goal the report captures the number of fatals, errors and warnings. Also captured are any waivers that were applied during the analysis in the interest of transparency. Again user defined success criteria for tolerance to fatals, errors and warnings is used to report the pass/fail status. Additionally each quality goal has a hypertext link to the more detailed SpyGlass report for users to double click on the exact violations reported by the DashBoard.
9IP Specification/Datasheet Report TSMC IP Kit generates the SpyGlass DataSheet report capturing key design specifications and profile statistics, once all goals run are finishedDesign ReadDesign Setup CheckDesign AnalysisIPPackaging
10Sample Results from TSMC IP Kit Analysis IPStatsCDCTestSDCPowerGate CountInstance CountFlop CountUnsynchronized CDCsSynchronized CDCsTestTest% ports constrained% registers constrainedNo. of unverified FPNo. of unverified MCPInternal (mW)Leakage (uW)Switching (mW)Core-1 21885 8817 462130229894.3100472.92.3Vendor A46637362128885.36535079Vendor B639021227585890722027406269992.38123288015Vendor C -IP15700023000253727575798.721113.94.9Vendor C-IP2950003900090004279138791.2894021.7Vendor C-IP31100004700048062552380294.11224.2Vendor D-IP1 489245940234791.81181870115Vendor D-IP29073032102015912512191117814020Vendor E-IP170439201254546130052399.794.989.4664.20.95…30+ Soft IPs qualified from 20 different IP vendors enrolled inthe TSMC Soft IP 9000 Program so far….
11TSMC IP Kit – A Typical User Adoption Flow LegacyIPNewRTL blocks3rd party IPIP SuppliersTSMC IP KitSTANDARDIZED IP INSPECTIONAtrenta DataSheetAtrenta DashBoard+IP design intentIP1IP1IP1IP1IP1IP1LegacyIP blocksNew RTLblocks3rd party IPHIGH QUALITY IPBLK 1BLK 2SoC IntegratorsBLK3BLK nMINIMIZE ITERATIONSSMOOTH SoC INTEGRATIONSoC
12TSMC IP Kit – User Benefits Standardized inspection flow for all IPs including ones from internal sources (new, legacy, older designs) Maximize internal IP re-usePropagate IP design intent – SDC/SGDC, waivers, *PF, … for chip integration IP integrates efficientlyBeyond functional verification…Verify IP for CDC, SDC, DFT, *PF, … Fully verified IPAutomated regression flow runs the IP kit nightly and generates DataSheet & DashBoard reports Automatically track IP updates/ bug fixesReview DataSheet and DashBoard to select the correct IP IP selection based on objective quality & spec metricsCreate an IP repository with published reports Streamline IP delivery and track usage
13Summary / ConclusionSpyGlass, TSMC Soft IP Quality Golden/GuideWare Rules and Atrenta Design analysis reports(DashBoard/DataSheet) together provide a comprehensive, detailed and design objective based Soft-IP quality assessment report.TSMC and Atrenta have partnered to adapt these tools for TSMC’s soft IP Qualification Program.A comprehensive set of quality checks, as included in TSMC IP Kit, has been defined and documented in Design Metric Reports.TSMC IP Kit Flow successfully adopted by 20+ IP ecosystem partners, which was quite helpful in improving the implementation readiness for their various Soft-IPs.Summary results of IPs for IP ecosystem partners are posted on TSMC Online