1. Centre for Development of Advanced Computing Software Defined Radio & Cognitive Radio: Implementation Initiatives KRISHNA KUMAR S. Centre for Development of Advanced Computing krishku@cdac.in

2. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 2 of 60 C-DAC A National Centre of Excellence and premier R & D institution under DIT, MCIT, Govt. of India involved in the design, development and deployment of Electronics & IT- based solutions for human advancement

3. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 3 of 60 10 Locations 14 Centres 3000 members

4. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 4 of 60 TETRA VoIP Digital Audio Software Defined Radio Networking TETRA-WiMax MANET CR CNM NG WF SDR AM/FM Radios & Television Alpha Numeric Information Displays CCTV Cameras Monitors Direct Reception System Multifunction mono/stereo Audio Consoles CD Players Equalizers Monitoring Amplifiers Digital Audio Work Stations 1990 2000 2010 2015 Broadcast & Communications @ C-DAC

5. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 5 of 60 2004200620072008 2009 2010/11 Study Report SDR Demos- 2 SCA WFS C-DAC SDR proposal 1 st SDR Project SDR PoC DIT 2012 2013 SDR Manpack Handheld SDR-NC C-DACSDR-DemoDITC-DACNAVY CR C-DAC SDR programme road map

6. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 6 of 60 recent/current projects in SDR/CR SDR for Naval Communication (DRDO) SDR Manpack (DIT) SDR Handheld (Core funding) Cognitive Radio Networks (DIT) jointly with IISc. Next Generation Waveforms for SDR Related projects Mobile Adhoc NETworks (MANET) Autonomic Network Management Systems (ANMS)

7. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 7 of 60 Demonstrated re-configurablity with two SCA compliant waveforms o TETRA UHF band & Military o Legacy FM Radio (VHF band) Clear Mode the PoC SDR lab model

8. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 8 of 60 SDR manpack: product perspective

9. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 9 of 60 agenda introduction SDR architecture SDR waveforms from SDR to CR Spectrum Sensing Engine application scenarios conclusions

10. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 10 of 60 Software Defined Radio a radio in which some or all of the radio’s operating functions are implemented through modifiable software or firmware

11. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 11 of 60 SDR Platform Consists of  Hardware,  Firmware,  Operating system  Middleware Takes different personalities, defined by the waveform that is loaded

12. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 12 of 60 SDR platform architecture

13. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 13 of 60 RF transceiver

14. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 14 of 60 Hopping Synthesizer

15. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 15 of 60 Harmonic Filter Bank

16. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 16 of 60 Baseband Boards

17. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 17 of 60 agenda introduction SDR architecture SDR waveforms from SDR to CR Spectrum Sensing Engine application scenarios conclusions

18. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 18 of 60 Waveform: Definition From http://www.wirelessinnovation.org/Introduction_to_SDRhttp://www.wirelessinnovation.org/Introduction_to_SDR The set of transformations applied to information to be transmitted and the corresponding set of transformations to convert received signals back to their information content. Representation of a signal in space The representation of transmitted RF signal plus optional additional radio functions up to and including all network layers.

19. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 19 of 60 Waveform Can be visualized at different levels Architecture  Conceptual entity  Defines and abstracts the waveform functions  Almost independent of the platform specifics Implementation  Physical realization of architecture  Closely related to platform

20. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 20 of 60 Waveform Architecture design What it is? What it is not?

21. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 21 of 60 Technical Specifications Candidate Architecture Architecture design process SIMULATION User behavioural patterns operational needs Radio Standards Final Architecture

22. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 22 of 60 Waveform Implementation Physical realization of architecture Closely related to platform Implementer should know  Overall platform architecture  Availability of Computing elements GPP, DSP, FPGA  Other configurable resources clocks, vca, vco, tunable filters etc.

23. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 23 of 60 Task Partitioning among CEs GPP  Signaling and control  Higher layer and MAC functions  PHY Bit level processing  Symbol rate processing  Soft real-time numerically intensive tasks – e.g. channel estimation  Ideally all hard real time PHY functions  Tasks best implemented using parallel architecture  Symbol rate processing for wideband systems DSPFPGA RULES OF THUMB

24. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 24 of 60 What devices in a given SDR? Device architectures are being upgraded constantly New FPGAs realize DSP functions using specific architectures New DSPs use hardware accelerators to implement hard real time tasks GPP performance too scales up Blurred boundaries! Vanishing boundaries? Platform designer priorities do matter

25. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 25 of 60 Portability & Re-configurability Probably the most important features of SDR Waveform should be portable across platforms [a statement to be qualified] Waveform should be able to configure and control platform resources Ensured by proper design and implementation of Waveform and Platform May result in sub-optimal implementation  but that’s okay! in most cases

26. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 26 of 60 Application Program Interfaces Key enabler in ensuring portability & re- configurability Abstracts low level functions Platform provider to facilitate platform abstraction through APIs Waveform implementer to use APIs to access platform features

27. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 27 of 60 GPP & DSP APIs GPP API calls are typically POSIX calls DSP API calls are C-function calls  API implemented as a library  API to be used while building DSP image

28. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 28 of 60 RF APIs To abstract Radio functions  Tuning LO  Configure Tx. DAC  Configure AGC  Etc. API calls are pre-defined messages Processed and executed by a dedicated controller

29. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 29 of 60 FPGA: Wrapper Equivalent of API for FPGA Wrapper defines the platform logic Waveform logic defines the (part of) PHY signal processing Waveform logic to be integrated with wrapper

30. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 30 of 60 Waveform Logic EMIF Glue SPI Glue McBSP Glue uPP Glue ADC FIFO DAC FIFO UART Glue UART Glue GPIO (Push Buttons, LEDs, DIP Switches, GPIO Headers) GPIO (Push Buttons, LEDs, DIP Switches, GPIO Headers) DSP ADC DAC RF Control UART Port FPGA IO Ring TOP module SPI Signals EMIF McBSP uPP 14 bit 16 bit Interrupt 1 Interrupt 2 FPGA: Architecture

31. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 31 of 60 FPGA: model based design To design waveform signal processing Can be done in a graphical way Designer need not no low-level architecture of the device Can be used jointly with Matlab/Simulink or similar simulation environments

32. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 32 of 60 FPGA: model based design tools Xilinx - System Generator Altera - DSP Builder Actel - Synplify Lattice - ispLever DSP Agilent system view – VHDL code generation

33. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 33 of 60 FPGA: integration with wrapper Combine the HDL source level Combine the wrapper source with waveform netlist  Similar to adding a library Combine at bitmap level  Wrapper logic implemented in advance  Waveform logic added using partial reconfiguration

34. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 34 of 60 agenda introduction SDR architecture SDR waveforms from SDR to CR Spectrum Sensing Engine application scenarios conclusions

35. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 35 of 60 from SDR to CR A natural evolution CR, by nature, has to be an SDR but, an SDR with certain specific fetures.

36. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 36 of 60 CR additional requirements A truly wideband radio front end Support for White/Gray space detection  Spectrum sensing - hardware & software  Geo-location and Database IEEE 802.22 Dynamic Spectrum Management  Channel & Bandwidth allocation  Rate adaptation & Tx power control

37. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 37 of 60 from SDR to CR: concerns Algorithm complexities – of course A truly wideband radio front end  Tx side RF Power amps  Rx side – wide band sensing AD/DA conversion bottle-necks Noise, sensitivity, interference protection, SFDR

38. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 38 of 60 agenda introduction SDR architecture SDR waveforms From SDR to CR Spectrum Sensing Engine – design & implementation application scenarios conclusions

39. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 39 of 60 Primary Signal Details Primary: Terrestrial analog TV txn in India System: CCIR system B,G PAL Bands: Band II VHF: 174 to 225 MHz Band IV UHF: 470 to 582 MHz Channel BW: 8 MHz

40. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 40 of 60 Requirements Incumbent Detection Threshold:  -94 dBm (measured at peak of sync) Channel Detection Time:  <=2 sec per channel Detection Performance:  Probability of Detection >=90% at False Alarm rate of <= 10% Guided by IEEE 802.22 WRAN WG interim recommendations

41. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 41 of 60 Platform - Lyrtech SFF SDR

42. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 42 of 60

43. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 43 of 60 From SS Algorithm to SS Engine (from “recipe” to “dish”) Study of algorithm Study of hardware architecture Designing software architecture Optimal partitioning of algorithm Model based design / C-program development Fixed point considerations  dynamic range, bit growth, over/under-run, truncation error Defining and realizing interfaces Debugging, testing and optimization

44. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 44 of 60 Detection Scheme Pre-processing/Feature extraction stage  Extracts the spectrum around the picture carrier Energy Detection stage  Computes the energy around the pictures carrier

45. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 45 of 60

46. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 46 of 60 Pre-Processing Decimating filter stages 5552 Digital IF BW: 8MHz 125 Msps 14 bits to sensing algorithm BW: 100kHz 500 Ksps 32 bits DDS @ 30MHz

47. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 47 of 60 Implementation Implemented in the FPGA part (Virtex 4) Design using Simulink / System generator  Model based design approach Fixed point implementation Word-length selection  bit growth  truncation error  resource utilization

48. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 48 of 60 Energy Detection N samples x B buffers Gives the adavntage of averaging Reduces the FFT implementation complexity

49. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 49 of 60 Implementation Implemented in the DSP (TMS320C64X) Code developed in C language Debugged using Code Composer Studio & XDS560 ICE A fixed point implementation Word-lengths selection

50. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 50 of 60 User Interface

51. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 51 of 60

52. Centre for Development of Advanced Computing Lab Setup

53. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 53 of 60 Test Settings Picture carrier: 67.25MHz Channel Bandwidth: 8MHz Video pattern: White Sensing duration: 20.4 ms Sampling rate: 125Msps Ensemble size: 1e5 SNR values: -30dB, -27dB, -24dB

54. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 54 of 60 PAPR for ATV Courtesy: Martyn J. Horspool, Analog-to-digital Upgradeable Transmitters For the Worldwide Market, Harris Corporation

55. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 55 of 60 Results

56. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 56 of 60 Results System meets the false alarm/miss detection performance at -27 dB SNR Highly encouraging result Enough margin to accommodate large scale fading Caveat: This is only a lab measurement

57. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 57 of 60 agenda introduction SDR architecture SDR waveforms from SDR to CR Spectrum Sensing Engine application scenarios conclusions

58. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 58 of 60 application areas Military PMR (public safety, police, paramilitary) Disaster management Commercial Cellular (Base Stations) Rural broadband access  IEEE 802.22 system adaptaion Tele-Medicine

59. Centre for Development of Advanced Computing 25 Feb 2012 sdr & cr: implementaion initiatives 59 of 60 acknowledgements Simon Zachariah Beena K. T. S. Sagar Chandra R. Murthy Shine K. P. Satheesh Kumar S.

60. Centre for Development of Advanced Computing …thank you Questions ??