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Optimal-Complexity Optical Router Hadas Kogan, Isaac Keslassy Technion (Israel)

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Router – schematic representation Problem - electronic routers do not scale to optical speeds: Access to electronic memory is slow and power consuming. Data conversions are power consuming as well. Electronic to optic Electronic to optic … LookupSwitching Optic to electronic … Buffering Router

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Power consumption per chassis [Nick McKeown, Stanford]

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How about an optical router? No electronic memory bottleneck No O/E/O conversions BUT: An optical router is thought to be too complex. Is it?

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Objective: quantify the fundamental complexity of an optical router

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Quantifying complexity “ Quantify the fundamental complexity of an optical router” reduce into most basic building blocks Switching – 2x2 switches (and input/output lines)

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Basic optical buffering component 111 (a)(b)(c) Buffering – 2x2 switches (and input/output/fiber delay lines) Mode of operation: (a) Write (b) Circulate (c) Read

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The complexity of a system is the minimal number of 2x2 switches needed to implement it.

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Quantifying complexity Complexity lower-bound: To get a state-space of size K in time T, the minimal number C* of 2x2 switches needed is: Examples: NxN switch: Time Slot Interchange with time frame N: 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 12345678 N 12345678

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Quantifying complexity A construction algorithm is said to be optimal if its number of 2x2 switches grows like the construction complexity. Examples: NxN switch (“Benes is optimal”): Time Slot Interchange: [Jordan et al. ‘94]. [Benes ‘65]

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Optimal buffer emulation

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Emulation definition 654321 t Original buffer: Buffer emulation (with delay D): 654321 t D

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Emulation idea Objectif: emulate buffer of size B Universal buffer: any policy Idea: schedule using frames of size B During any frame of B slots, observe which packets leave the original buffer and color them in blue After some pipeline delay, send these blue packets in the same order Optical buffer F - Frame of size B Frame-based scheduling

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Algorithm B departure Algorithm is optimal Complexity Θ(ln B) Complexity lower-bound Θ(ln B) (the Time Slot Interchange is a special case) 6 3 1 2 5 4 6 3 1 6 3 1 2 5 4 1 2 4 3 5 6

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Optimal router emulation

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What we want: an ideal router An output-queued push-in-first-out (OQ- PIFO) switch. OQ - Arriving packets are placed immediately in the queue of size B at their destination output. PIFO – packets departure ordering is according to their priority. Input 1 Input N … … Output 1 Output N

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What we want: an ideal router Why it is ideal: OQ: Work-conserving best throughput and average delay. PIFO: Enables FIFO, strict priority, WFQ… But – up to N packets could be destined to the same output: Speed-up for switch Speed-up for queue PIFO is hard to implement.

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Finding the complexity Direct calculation of complexity seems impossible – what are the states? Alternative way of finding the complexity: Find a lower bound Find an upper bound via algorithm Algorithm complexity = Θ (lower bound) algorithm is optimal

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Lower bound - intuition Input 1 Input N … … Output 1 Output N At least Θ(Nln(N)) At least Θ(ln(B)) B Intuition: the complexity of an OQ-PIFO switch is at least Θ(N ln(N) + N ln(B)) = Θ(N ln(NB))

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Lower bound A frames switch (time/space switch): 341 625 1278 11910 t=3t=4t=5t=6t=7t=8t=9 456 123 101112 789 t=1t=2t=3t=4t=5t=6 Frames switch A frames switch is a special case of an OQ-PIFO switch. The practical complexity of a frames switch: Complexity {OQ-PIFO} ≥ Θ(Nln(NB)) Now, find an algorithm that reaches this lower- bound B N

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Example: Emulating a non-idling OQ-FIFO switch : Solving the speed-up problem Using parallel buffers to resolve conflicts: At most one packet can enter a buffer at each time slot (N-1 constraints). A packet departing at time T should not enter a buffer with a packet departing at T (N-1 constraints). 2N-1 buffers are enough. Input 1 Input N … Output A … A1A1 C1C1 A2A2 Output B … C2C2 D1D1 X X Leaves output A at time 1

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The pigeonhole principle Proof intuition: Pigeons ↔ Packets Holes ↔ Buffers For emulating PIFO behavior – The departure process is slightly modified 4N-2 parallel buffers are required Input 1 Input N … … Output 1 Output N …

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… Output 1 Output N … An optical emulation of an OQ-PIFO switch Optical buffer Optical buffer The pigeonhole principle + Our emulation of an optical buffer = An optical OQ-PIFO switch

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πBπB B B πBπB (4N-2)xN switch πBπB B B πBπB πBπB B B πBπB... Nx(4N-2) switch An optical emulation of an OQ-PIFO switch Number of 2x2 switches= Θ(NlnN+NlnB) = Θ(Nln(NB)) = Θ(lower bound) algorithm is optimal

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Conclusion Buffer fundamental complexity = Θ(lnB) OQ-PIFO router fundamental complexity = Θ(NlnNB) Both can be reached using given algorithms

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Thank you!

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