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Fast position resolution silicon detectors OUTLINE General properties of position sensitive detectors Column Parallel CCD (CPCDD) Monolithic Active Pixel.

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Presentation on theme: "Fast position resolution silicon detectors OUTLINE General properties of position sensitive detectors Column Parallel CCD (CPCDD) Monolithic Active Pixel."— Presentation transcript:

1 Fast position resolution silicon detectors OUTLINE General properties of position sensitive detectors Column Parallel CCD (CPCDD) Monolithic Active Pixel Detectors (CMOS imager) Depleted Field Effect Transistor Detectors (DEPFET) Hybrid Active Pixel Detectors (HAPS) Gregor Kramberger, DESY

2 n-Si U p+p+ n+n+ U up to 1 mm p+p+ n+n+ n-Si U up to 1 mm n+n+ p+p+ Signal Position can be determined – center of gravity Particle trackingImaging each particle leaves a track Only some photons interact U up to 1 mm Signal 3.6 eV/pair collection time ~ns order To obtain good position resolution – high S/N ratio

3 Segmentation options: low particle (photons) rate – strip detectors Bottom side perpendicular segmentation or two detectors (each 1D) can be used! N M Read-out channels/detector module: N+M When read-out in: series: N+M time units parallel: bigger of [N,M] Only projections can be obtained. M N high particle (photons) rate – pixel detectors Read-out channels/detector module: NxM When read-out in: series: NxM time units parallel: bigger of [N,M] Usually many detector modules are put together to cover the image area! (silicon is produced in silicon wafer – nowadays already 8” inch)

4 Detectors diced out of silicon wafers Similar processing as for microelectronics lithographic steps, etching, implantations, PolySi filling 15 cm diameter >1m Slicing the rod in typically 300  m slices (wafers)

5 What do we want from one module? A large high resolution “picture” as fast and easy as possible! few  m few 10 cm 2 picture taking rate (frame rate) up to few 10 kHz without severe restriction on operating conditions, electronics (voltage supply etc) needed With a lot of effort can be achieved! One of the following requirements can be even more demanding on expense of the others! Many common points: with modification same detector concepts can be used for both This talk will try to illustrate different detector options for particle tracking at LC and to some extent their ability to be exploited for X-ray detection! The further discussion will refer only to pixel detectors!

6 Charge Coupled Devices (CP CCD) (RAL, Oxford, Liverpool) Active Pixel Sensor (APS) - Depleted Field Effect Transistor Detector (MPI München, Mainz, Bonn) - Monolithic Active Pixel Sensors (MAPS, CMOS imager) (IRES Strasbourg, DESY, NIKHEF) - Hybrid Active Pixel Sensors (HAPS) (Warshaw, Krakow, Insubria) (widely used technology for pixel detectors in HEP) Division of fast position sensitive detectors with respect to operational principle! One can not explain everything -> only the concepts will be presented ! things specific to tracking at LC (material budget – thinning of the detectors, power consumption, mechanics, cooling … will be left out) Different collaborations working on LC vertex detector (plots taken from their presentations)

7 CPCCD - Principles of operation buried channel CDD potential minimum moved from the surface by n + collected charge is a combination of drift and diffusion (drift much faster – high resistive epi-Si) p/p + edge works as a reflection layer MOS gate is superimposed on top of the n + layer the depleted region is controlled by the voltage applied to the electrodes (p 1,p 2,p 3 ) CCD is an array of capacitors PNP CDD Instead of MOS a p-n-p structure is formed Larger volume can be depleted and by that higher photon detection efficiency at larger energies ( used for XMM – Newton ) oxide metal gates p1p1 p2p2 p3p3 Fully depleted n - bulk p1p1 p2p2 p3p3 p+p+ p + implants V p + (bulk) dep. p (epi) U

8 CPCCD - Readout Asymmetrical n + doping Only one direction of charge transfer possibleboth direction of charge transfer possible sine clocks p1p2p3p1p2p3 p1p2p1p2 V

9 Classical CCD: slow – not appropriate for high frame read-out rates factor 2 in speed “Classic CCD” Readout time=NxM/ out different frequencies can be used in horizontal shift register reset Source follower (1 st stage of amplification) 2 nd stage amplification follows One can use higher frequency in horizontal shift register – some gain in speed, but not enough! Typical frequency 5 MHz Different solution is needed!

10  m pixels  m pixels 1.3 cm 10 cm CCD VXD read-out  m pixels 1 st layer ladder read-out TESLA VXD – requires 50  s read-out/frame in layer 1 – huge challenge ! read-out of column with ~2500 pixels (10x1.3 cm 2 ) in 50  s (20 kHz frame rate) S=13 cm 2 Fast readout speed only with Column parallel readout new design – first in the world ! Serial register omitted 50 Mpixels/sec from each column Image section clocked at high frequency Each column has its own ADC/amplifier (compare to classic CCD) “Column Parallel CCD” Readout time=N/ out

11 imagine feeding large capacitance (2-3 nF/cm 2 ) at 50MHz: Low resistivity gates are required - Polysilicon gates replaced by metallized gates (30% variation in clock amplitudes over CCD - simulations) Low voltage clocks up to max. 3 V amplitude - to reduce the power heating high resistive epi-Si to have large area depleted and therefore fast collection well capacity ~ e n + implant design to enhance charge transfer between cells +some other things …… Two phase, 50 MHz design pixel size 20 μm  20 μm; Metallized gates + field enhance implant Metallized gates PolySi gates + field enhance implant PolySi gates SF DC wire bonds World’s 1 st CPCCD prototype fully designed and operational at 50 MHz Fast CPCCD – considerations

12 Source follower ( needs reset ) or Direct Coupling ?  Both charge and Voltage amplifier for DC or SF coupling  5 bit flash ADC  buffer FIFO Read-out chip (CPR-1 chip, 0.25 mm CMOS, 50 MHz) FIFO bit flash ADCs Charge Amplifiers DC Voltage Amplifiers SF Wire/bump bond pads Next iterations will have also: Gain eq. between columns, CDS, clustering,data sparsification

13 Charge losses must be very small: CTI~ with n=2000 Q/Q 0 =82% How to reduce CTI: 2-phase CCD (smaller V) notch CCD –additional implant (smaller V Q sees less traps) fast CCD (Q has no time to get trapped) – implementation field enhanced implants pre-injection of dark current to fill the traps proper operational temperature TRAPS  - imperfections in Si crystal (capture charge during transfer) Charge collection efficiency (generated charge clocked through the detector) CTI denotes the loss of charge when shifted from one cell to another Problem of CCDs radiation induced – radiation damage

14 CPCCD - Prototype performance Previous prototype – off-shell 3 phase CCD driven at 50 MHz at –70 with pp 3V amplitudes 55 Fe spectrum

15 Pros CP-CCD Proven technology – a lot of experience with low resistive epi-Si or PNP-CCD large effective thickness can be reached – good for imaging large homogeneity of charge collection small pixel sizes of order (20x20  m 2 ) – good spatial resolution < 5  m Cons CP-CCD High costs and limited vendor choice ( only MTech is working on them ) Radiation hardness is questionable (charge transfer over entire detector – CTI degradation) detectors may need to be operated at lower temperatures

16 MAPS (CMOS imager)- principles of operation 15 µm double-well CMOS process with epitaxial layer the charge generated by the impinging particle is reflected by the potential barriers due to doping differences and collected by thermal diffusion by the n-well/p-epi diode large charge spreading (signal shared over many pixels) “slow” charge collection (t~100 ns – depends on epi-Si) integration of the circuitry electronics on the same sensor substrate (1 st stage of amplification) useable for detection off photons with few keV (limit set by epi-layer thickness) through the center of N well through the center of P well fill factor = 100% -no HV -operation voltage set by CMOS process

17 Relaxation of excess charge after particle passage 0 nsec 1 nsec 10 nsec 20 nsec Particle track If  of the substrate is high significant contribution of diffused charge from substrate to the total charge 0 nsec 1 nsec 10 nsec 20 nsec

18 MAPS - Readout Collection (int. time=frame rate) OutputReset… Reset (common row) M2 gate potential

19 Simple readout scheme for the first prototypes (5 up to now) a reset cycle (all pixels) – common row reset cell output is amplified - physical signal: two frames are read-out and subtracted – CDS Last amplification stage common to all Current prototype’s clock speed 40 MHz At present prototypes only reset and clock signals are needed Full analog information (all pixel) is read-out in series - slow

20 Signal/Noise ratio for given event CDS : get rid of FPN, reset noise, 1/f noise

21 MIMOSA 6 (being manufactured) pixel pitch 28x28  m 2 1 array 30x128 pixels – 29 transistors/pixel – instead of 3 New features: columns read-out in parallel - max. clock freq.: 30 MHz (CP) Also 2 nd stage amplification and CDS done on-pixel! ADC conversion done at the edge of columns data sparsification integrated at the edge off the chip – zero suppression Chip layout Single pixel layout AC coupling capacitor Charge storage capacitors “Large” pixel size and deep submicron technology -> integration of high chip functionality CP read out 6 clock cycles for row

22 ~5-8 clock cycles will be needed for processing the signal for each pixels in each column R/O parallel to the short side of the detector: for TESLA ~ 200 pixel (0.5 cm)/50  s pixels Analog and digital electronics pixels Analog and digital electronics optimistic less optimistic Column read-out 10 cm ~1 cm 1 st layer ladder read-out

23 chip size 1.73x1.73 cm 2 Wafer view MAPS – prototype performance 5 prototypes build so far in different technologies (deep sub  ), different pixel sizes, clock frequencies and epilayer thicknesses MIMOSA 5 – large size detector - standard 0.6  m CMOS of AMS with 14  m thick EPI layer (10 14 cm -3 ), pixel 17x17  m2, well capacity > e First stitched ladders of few neighboring chips are produced (100  m between chips – can be reduced to 1  m – almost no dead area) simple serial frame read-out – 150 Hz frame rate (full analog information read-out) problem with fabrication yield! Pixel read-out direction ~10% of the total surface max. CMOS die size 2x2 cm 2

24 55 Fe calibration

25 To large extent leakage current contribution (shorter frame rate should reduce noise to around 10e) T=0 o C Large scale prototype test in pion beam

26 Pros MAPS low cost (production of 6 6” wafers for example Euros, 9 USD/cm 2 is expected) standard CMOS process – profiting from huge progress in microelectronic industry: convenient way of design - standard software tools, design kits and libraries, high yield, low power consumption Radiation hardness – up to few 100 kRad less than 10% degradation in collected charge low noise due to small gate capacitance (few fF) – theoretically few e - few 10 e signal processing (1 st and 2 nd stage amplification) in each individual pixel is possible -> good S/N at high speed homogeneity of charge collection >97% pixel sizes of order (25x25  m 2 ) – could be limited by integration of large number of transistors Cons MAPS limited epi-layer thickness and by that usability for detection of photons (deep sub  maybe no epi) requirement for 8 metal layers and also analog design rules for CMOS – not very easily found potential danger of very deep sub-micron technology (trench isolation – charge trapping)

27 p-channel JFET or MOSFET integrated on high-ohmic, sidewards-depleted, n-substrate a local potential minimum is formed by S/D potentials aided by a deep n implantation (punch-through bias of the pixels) electrons are collected in an internal gate close to the surface (collection time few ns) the transistor channel current is modulated by charge collected in the internal gate the device can be switched on/off by an external (top) gate DEPFET - Principles of operation

28 pulsed clear: pixel dead time < 1% of measuring time Internal gate fills up with: signal charges thermally generated charges (leakage current)

29 random access to pixels ! DEPFET - Readout DEPFET Column parallel read-out mechanism: switch on one row through gate contacts and take pedestal current + signal current reset the row switch row on again and take pedestal current subtract the signal-pedestal repeat for all rows do CDS Now: 20  s – 50 kHz TESLA: 20 ns – 50 MHz a very ambitious but achievable goal Electronics requirement Current read-out drain) Current memory cells

30 Using different readout scheme the frame read-out time can be reduced to as low as 10  s (100 kHz frame rate) Drawback is larger power consumption: expected noise < 100 e (at root temperature) with resolution of < 5  m current prototype development: 128x128 pixels array clocked at 50 MHz

31 DEPFET – prototype performance DEPFET’s field of use – beside tracking in particle physics: low energy X ray astronomy XEUS ( keV sensitivity) Medical imaging (autoradiography) - BIOSCOPE (64x64 pixel array of 50x50  m 2 ) single pixel device ENC=4-5 e matrix – 69 e (35 o C) 1 kHz frame rate - 50 kHz line 55 Fe (6 keV) - 37 lp/mm ~ 6.7  m 109 Cd (22 keV) - 57 lp/mm ~ 4.3  m 75  m tungsten plate Imaged with sources projections 6  threshold

32 Real time – space and energy resolution! (different markers can be separated)

33 Pros DEPFET low noise due to small gate capacitance (few 10 fF) – theoretically few e external amplification only in the 2. stage what leads to good signal/noise the thickness of the substrate can be large - higher efficiency for photons! Homogeneity of charge collection >95% (achieved with prototypes so far) pixel sizes of order (25x25  m 2 ) Non-linearities < 0.1% within large dynamic range Radiation hard (deep submicron technology, rad-hard design rules) ????? Drawback High cost (8 implantations, 15 masks, 200 technological steps) less flexible – not suitable for any vendor

34 HAPS - Principles of operation chip sensor fast read-out (charge collection times of ns order) each pixel has its own read-out amplifier Detection of low-energy photons from the back – large thickness – up to 1 mm - can be depleted The read-out chip is mounted directly on top of the pixels (bump-bonding) Problem is in assembly of pixel detector-hybrid: bump bonding – alignment This limits the pixel detector resolution – minimal bump-bondable size – pixel area limited by the read- out chip! Large pixel capacitance – higher noise BUT…, no limit on read-out chip design possible to detect few keV photons from the back p+p+ n+n+ n-n- All major HEP experiments concept At LHC MHz frame rate – with noise around 200 e Charge sensitive preamplifiers

35 readout pitch = n x pixel pitch Large enough to house the VLSI front-end cell Small enough for an effective sampling and good spatial resolution Charge carriers generated underneath one of the interleaved pixel cells induce a signal on the capacitively coupled read-out pixels, leading to a spatial accuracy improvement by a proper signal interpolation. Silicon On Insulator (SOI) detector Detector  handle wafer –High resistive –300  m thick Electronics  active layer –Low resistive –1.5  m thick Pixel detector with interleaved pixels Detector: conventional p + -n, DC-coupled: Electronics: conventional bulk MOS technology INSULATOR SUCIMA

36 Interleaved Readout Max charge loss ~ 40% In good agreement with estimated values for capacitive network HAPS - Prototype performance 60  m cell size = 100  m The read-out pixels were wire bonded to the readout electronics chip. The BELLE experiment amplifiers and readout chain were used 880 nm laser used to determine CCE <80  m spot size – scan performed with 2D stage Resolution between 3-10  m

37 Pros HAPS Proven technology – a lot of experience Very fast - up to few MHz frame rate good homogeneity of charge collection no problems with radiation hardness (can sustain 3 orders of magnitude larger doses than others) large thickness can be depleted – good efficiency for photons Independent design of the read-out chip Cons HAPS High cost (ATLAS and CMS estimation) Complicated assembly – alignment of hybrids and detectors higher noise (large pixel capacitance)

38 SUMMARY There is a bright future for silicon in the field of particle detectors! With new ideas coming and microelectronics industry growing … sky is the limit


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