1. Project outline  EMCROSS - European Multicore Cross-Domain Architecture  Jürgen Meilinger, Airbus Defence and Space, Emcross@cassidian.com  Cross-domain project proposal

2. Project context  Electronics and Software content emerging  Focus on highly automated and autonomous systems  Processing power needed in context of safety critical and certifiable environments

3. Overview Hardware solution: New or modified Multicore processor Implementing certifiable architecture FPGA solution: Implementation of proven architecture in FPGA, using performant cores Software solution: Shift task of “determinism“ into the SW statements (“execution time”) Certifiable multicore processor approach for mixed criticality applications

4. Workstream “Chip” Based on existing MultiCore chips with promising architecture the design shall be modified in such a way, that the chip is acceptable to the certifying authorities for use at least in DAL C applications. All requirements and results from preceding projects shall be re- used for the new implementation. Advantage: Proven design basis and architecture Risk: Performance upgrade only with new processor

5. Workstream “FPGA” New generations of FPGA are becoming available in a quality that will be useable for safety critical applications. A suitable architecture – based for e.g. on ACROSS project – shall be investigated for implementation in an FPGA, using suitable high performance cores suitable also (cost wise) for the limited quantities required in avionics and even for automotive applications. Advantage: Suitable for limited quantities Risk: Performance of implementation unclear

6. Workstream “Software” The problem if using Multicores is the missing determinism in the complex and not under our control architecture. A solution might come through the introduction of a suitable “execution time” notion into the programming. Such approach was already developed by as part of “X-Giotto”. If a suitable COTS MC is used, this approach could lead to a good solution for certification. Advantage: No expensive development of chips Risk: Performance of implementation unclear

7. Consortium status  Consortium in formation  OEM and TIER 1 available  Semiconductors in evaluation  Academia and research partially available