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LEAKAGE and TAMPER Resilient Random Access Machine (LTRAM) Pratyay Mukherjee Aarhus University Joint work with Sebastian Faust, Jesper Buus Nielsen and Daniele Venturi

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Provable security breaks down! Because…. The ModelReality

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Provable security breaks down! Because…. The ModelReality More seriously ! Side channel attacks: Leakage/ Tampering Blakcbox Our main focus

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Models of Tampering Tamper “only memory” Tamper “whole computation”

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Models of Tampering Tamper “only memory” Tamper “whole computation” In the beginning…. We are STRONGERrrr !!!

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Models of Tampering Tamper “only memory” Tamper “whole computation” Existing results suffer from limitation e.g. can tamper upto 1/poly(n) A number of strong positive results e.g. split-state tampering …..after a few years…. [IPSW 06, ….., DK 14] [GLMMR 04, ……………………………..,DPW 10,…..] I have better RESULTS !!!

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Our approach Can we protect against more Tampering with computation if we consider RAM ? Instead of Protect me !

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Our Result: RAM + NMC => TRAM TRAM TCC 2014 Idea: Encode locations with NMC. Note: The computation is stored as a program.

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In fact we can get LTRAM LTRAM Caveat: We assume tamper-proof CPU. But, the CPU is small and universal i.e. independent of the functionality.

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Our LTRAM CPU Secret Disk-1 Secret Disk-2 Public disk

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