Presentation on theme: "-Kavyashree Pilar. ● Implementation of parity bit generator and checker circuit. ● Project deliverables: – Schematic – Worst case timing analysis – Power."— Presentation transcript:
● Implementation of parity bit generator and checker circuit. ● Project deliverables: – Schematic – Worst case timing analysis – Power and thermal analysis – Hardware implementation and functionality verification.
Random data generator: Pseudo-Random noise generator circuit Parity bit generator : Generates a logic high parity bit when odd number of data bits are on logic high state. Channel : Represents noisy environment which can alter one or more data bits and the parity bit. Parity checker: Generates a new parity bit using the data bits and compares it with the parity bit received with data.
● ICs used: ● 74AC164 : 8 bit shift register ● 74AC86 : Quad 2-input ExOR gate ● PCB Board Specification: ● Standard board : 10mils thick with copper routing layers on top and bottom.
● Trise_min= 3ns ● F_knee = MHz ● AC coupling capacitor value = 100pF ● Length of rising edge(L) = ” ● L/4 = ” ● Longest trace length ~ 5” ● No termination required
PNR data generator tPLH of U1 = 12.5ns tPLH of U2 = 10.8ns Q5-Ex-or input = Ex-or output – B = Setup time for U1= 2.5ns Minimum clock period = ns Maximum operating frequency =36.76MHz
● U1: 74AC164 ● Each output drives 2 ExOR gate inputs ● Q5 and Q6 drive one more ExOR gate ● CPD= 150pF, Ci = 10pF, assume f = 36MHz ● Vcc=5.5V,Ic=3mA ● Pd = 234.3mW ● θJA = 70 0 C/W ● Junction temperature = C ● MTBF is very good – No cooling required.
All ExOR gates except U5 drive 4 ExOR inputs Cpd = 57pF Icc= 80uA Ci = 10pF Pd= mW θ JA = 70 0 C/W Junction temperature = C U5 drives 3 Ex-OR inputs: Pd = mW Junction temperature = C
Hardware implementation Functionality testing: Verification of parity bit generation circuit Verification of parity checker circuit
● PCB design using OrCAD capture/CIS and PCB editor. ● Issues faced and solutions: ● ORCAD capture – schematic done V6.6 demo version can not be modified with V6.3. ● Demo version can handle only upto 60 components. ● The following command can be used on command prompt can be used when netlist generation via GUI fails: C:\Cadence\SPB_16.3\tools\capture\pstswp -pst -d ".DSN" -n "allegro" -c "C:\Cadence\SPB_16.3\tools\capture\allegro.cfg"
CMOS design – analyze termination requirements before starting with the schematics.