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Xilinx FPGAs:Evolution and Revolution. Evolution results in bigger, faster, cheaper FPGAs; better software with fewer bugs, faster compile times; coupled.

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Presentation on theme: "Xilinx FPGAs:Evolution and Revolution. Evolution results in bigger, faster, cheaper FPGAs; better software with fewer bugs, faster compile times; coupled."— Presentation transcript:

1 Xilinx FPGAs:Evolution and Revolution

2 Evolution results in bigger, faster, cheaper FPGAs; better software with fewer bugs, faster compile times; coupled with better technical support.

3 Innovative architectural and circuit features with advancements in design methodology - modular team based design & internet based configuration method: resulting in Revolution.

4 A Decade of Progress

5 Xilinx FPGAs : An Endless Journey 1.5K 7.5K, 50MHz 85K, 80 MHz 100MHz+ 40K 16K, 50MHz 50K-1M, 200MHz 200K, 200MHz 4M, 250MHz 300K, 200MHz+ 40K-8M, 420MHz 10M, 420MHz

6 Xilinx FPGAs - Generic Features High Performance at different voltages Footprint Compatibility - Devices within each family are compatible. Low power consumption/high performance Integrated Software Technology independence - EDIF, VHDL, Verilog, SDF interfaces.

7 XC2000 First FPGA Family from Xilinx. Two members: XC Gates XC Gates Ext. Crystal Oscillator. No Tri State Buffers. XACT 1.0 Development System.

8 XC2000 Max.Logic Gates 1500 Max. CLB Flip-flop100 Max. I/O Pins74 Max. I/O Flip-Flop74

9 XC3000 Replaces TTL, MSI and other PLD logics. Integrates complete subsystem into single Package. System clock Speed up to 50 MHz. On-chip crystal Oscillator. Low-Skew Clock Nets. Over 20 different Packaging Options Interface to popular design Environment like Mentor, Cadence and View Logic.

10 XC3000 CLB

11 XC3100A Ultra-high-speed Family with six members. XC3195 in 22 X 22 CLB array size. Compatible with XC3000. Error checking of configuration bit stream.

12 XC4000 CLB

13 XC4000 Family Features Synchronous Single and Dual-Port RAM Internal Three-state buffers. JTAG Boundary Scan System performance to 80 MHz 0.5 µ SRAM Process Technology

14 XC4000 Sub-Families VersionMax. logic Max. I/O Voltage Gates XC4000XL 3k-85k XC4000EX 28k, 36k3205 XC4000E3.0-25k2565

15 XC5200 Low Cost FPGA Family. System Features: - Fast Arithmetic Functions - High Performance Clock Network - Highly routable - Easy Pin Locking - Fast wide Functions - Three-state buffers - JTAG - Performance up to 50 MHz.

16 Resource Comparison

17 Xilinx 4000 Series Heritage Total Cost Management Advanced Process Technology Small die size Low cost packaging Low test cost 100 MHz+ performance On-chip SelectRAM Software v4.2i Core solutions Xilinx Spartan/XL FPGAs

18 Total Cost Management Leading edge process technology Smallest die size of any FPGA with on-chip RAM Focused package offering Low-power architecture allows use of highest volume plastic packages Streamlined test flow Lower cost test hardware Built-in self test features and shorter test times Optimized manufacturing flows

19 Chip Combines 3.3 V operation with 0.25u benefits Spartan-XL Family Advanced 0.35m Process Transistor gates 0.35u Allows 3.3 V supply All other features 0.25u Small size Low capacitance Performance

20 Spartan Speed Grades Performance XC5200 XC4000E Spartan Spartan-XL E-1 E XL-5 XL-4 Higher speed grade = higher performance

21 What’s missing in Spartan? No asynchronous RAM Only RAM16(32)X1S, RAM16X1D, ROM16X1 No edge decoders No DECODEx No wired-AND No WANDx or WOR2AND Mode pins not usable as I/O No MD0, MD1, MD2

22 Virtex - features Densities from 50 K to 1M system gates. System performance up to 200 MHz. Multi-standard Select IO interfaces. Built-in clock-management circuitry - Four DLLs - Four Low-skew global Clock Distribution Net Hierarchical Memory System. Dedicated Multiplier Support.

23 Spartan-II - features Densities as high as 200K gates. Streamlined features based on Virtex architecture. Very Low Cost LUT Distributed RAM and Block RAM support. Dedicated Multiplier support. 4 DLLs

24 Virtex/Spartan-II CLB 1 CLB holds 2 slices Each slice has two sets of Four-input LUT Any 4-input logic function Or 16-bit x 1 RAM Or 16-bit shift register Carry & Control Fast arithmetic logic Multiplier logic Multiplexer logic Storage element Latch or flip-flop Set and reset True or inverted inputs Sync. or Async. Control

25 Virtex/Spartan-II DLLs Improve Clock Networks DLL1 DLL3 Deskew Clocks on Chip Manage Multiple System Clocks Deskew Clocks on Board Cascade DLLs Generate Clocks (Multiply, Divide, or Shift) Convert Clock Levels using Select I/O Delay locked loops synchronize on-chip and board level clocks DLL4 DLL2

26 Virtex-E – what’s added? Up to 4 million system gates 2-4X more Block RAM 8 DLLs Differential I/O signaling (LVDS/BLVDS) some new speed grades.

27 Spartan-IIE - features Density K Supports LVDS 4 DLLs VCCINT – 1.8V More speed grades than Spartan-II. Less packaging Options.

28 Virtex-II All Xilinx FPGAs contain the same basic resources CLBs contain combinatorial logic and register resources IOBs interface between the FPGA and the outside world Programmable interconnect Other resources Three-state buffers Global clock buffers Boundary scan logic Virtex-II devices contain additional resources Block SelectRAM Dedicated Multipliers Digital Clock Manager (DCM )

29 CLB Tile CIN Switch Matrix TBUF COUT Slice S0 Slice S1 Fast Connects Slice S2 Slice S3 CIN SHIFT

30 Slice Structure Slice 0 LUT Carry LUT Carry DQ CE PRE CLR DQ CE PRE CLR

31 Mult-AND and dedicated Multiplier too SRL16 DDR Registers. Fast Carry Logic Digitally Controlled Impedance

32 Connecting Function Generator F5 F8 F5 F6 CLB Slice S3 Slice S2 Slice S0 Slice S1 F5 F7 F5 F6

33 Select I/O Allows direct connections to external signals of varied voltages and thresholds Optimizes the speed/noise tradeoff Saves having to place interface components onto your board Differential signaling standards LVDS, BLVDS, ULVDS LDT

34 Distributed and Block Select RAM RAM16X1S O D WE WCLK A0 A1 A2 A3 LUT RAM32X1S O D WE WCLK A0 A1 A2 A3 A4 RAM16X1D SPO D WE WCLK A0 A1 A2 A3 DPRA0DPO DPRA1 DPRA2 DPRA3 Slice LUT

35 Dedicated Multiplier Block 18 x 18 Multiplier Output (36 bits) 4x4 signed~255 MHz 8x8 signed~210 MHz 12x12 signed~170 MHz 18x18 signed~140 MHz Eighteen-bit 2’s complement signed operation Optimized to implement Multiply / Accumulate functions Multipliers are physically located next to block SelectRAM

36 DCM Up to twelve DCMs per device Located on top and bottom edges of the die Driven by clock input pads DCMs provide: Delay-Locked Loop (DLL) Digital Frequency Synthesizer (DFS) Digital Phase Shifter (DPS) Digital Spread Spectrum (DSS) Up to four outputs of each DCM can drive onto global clock buffers All DCM outputs can drive general routing

37 Challenges to accelerate Processing performance Multiple Tasks Parallel Processing in Hardware Multiple Processors on Multiple Tasks Multiple Solutions High performance lower cost low complexity Specific task focus Scalable Parallel Processing Using Multiple Processors Very Large Single Task requires Parallel Processing Types of Challenges

38 Virtex-II Pro Addresses All Processing Tasks Up to four 300MHz PowerPCs for multiple processing Virtex-II Pro Fabric Fabric for parallel processing in hardware Up to four 300MHz PowerPCs for multiple processing Uunmatched Performance Uunmatched Flexibility Virtex-II Pro Fabric Fabric for parallel processing in hardware

39 Logic Capacity and Features

40 Virtex II Pro Leads all the way

41 Supply Voltage XC4000 and Spartan families use a 5V supply. The-XL families use 3.3 V supply. Virtex and Spartan-II use 2.5V supply. Virtex-E uses 1.8 V. Virtex-II and Virtex-IIPro uses 1.5 V

42 Xilinx Development System

43 THE FUTURE……. In 2005, FPGAs will be built on 70nm-Cu process; will implement 50 million system gates; with 2 billion transistors on-chip; with 10 layers of copper metal; with embedded processors running at 1 GHz clock rate; with direct interface to 10 Gbps serial data.

44 URLs Newsgroup comp.arch.fpga

45


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