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GPU Computing Dr. Bo Yuan

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1 GPU Computing Dr. Bo Yuan

2 Overview 2 Foundation GPUCUDAThread Memory Structure Intermediate Kernel Vector Addition Matrix Multiplication Shared Memory Advanced Warp Memory Access Resource Optimization Dynamic Parallelism Extension Floating Point Stream Multiple GPUs Parallel Matlab

3 What is GPU? Graphics Processing Unit First GPU: GeForce 256 (1999) Connected to motherboard via PCI Express High computational density and memory bandwidth Massively multithreaded many-core chips Traditionally used for real-time rendering Several millions units are sold each year. 3

4 Graphics Cards 4

5 GPU Pipeline 5

6 6 Rasterization

7 Anti-Aliasing 7 Triangle GeometryAliasedAnti-Aliased

8 GPGPU General-Purpose Computing on GPUs Massively Parallel, Simple Operations Suitable for compute-intensive engineering problems The original problem needs to be cast into native graphics operations. Launched through OpenGL or DirectX API calls Input data are stored in texture images and issued to the GPU by submitting triangles. Highly restricted access to input/output Very tedious, limited success with painstaking efforts 8

9 Trend of Computing 9

10 CPU vs. GPU 10 DRAM Cache ALU Control ALU DRAM CPU GPU Number of ALUs Memory Bandwidth

11 Power of the Crowd 11 SP SFU SP SFU Instruction Fetch/Dispatch Instruction L1 Streaming Multiprocessor Shared Memory SM –Streaming Multiprocessor –Multi-threaded processor core –Processing unit for thread block –SPs (Streaming Processor) –SFUs (Special Function Unit) SP –Streaming Processor –Scalar ALU for a single CUDA thread SIMT –Single-Instruction, Multiple-Thread –Shared instruction fetch per 32 threads (warp)

12 Need For Speed 12

13 Green Computing 13 Intel Core i7-980XE GTX 750 Ti GTX 680 GTX 580 GFLOPS per Watt

14 Supercomputing TITAN, Oak Ridge National Laboratory Speed: 24.8 PFLOPS (Theory), 17.6 PFLOPS (Real) CPU: AMD Opteron 6274 (18,688 × 16 cores) GPU: NVIDIA Tesla K20 (18,688 × 2496 cores) Cost: US$ 97 Million Power: 9 MW 14

15 Personal Supercomputer 15

16 What is CUDA? Compute Unified Device Architecture Introduced by NVIDIA in 2007 Scalable Parallel Programming Model Small extensions to standard C/C++ Enable general-purpose GPU computing Straightforward APIs to manage devices, memory etc. Only supports NVIDIA GPUs. 16

17 CUDA-Enabled GPU 17

18 CUDA GPUs 18

19 Fermi Architecture 19

20 Kepler Architecture GeForce GTX 680 (Mar. 22, 2012) GK104, 28 nm process 3.5 billion transistors on a 294 mm 2 die CUDA Cores: 1536 (8 SMs X 192 SPs) Memory Bandwidth: 192 GB/S Peak Performance: 3090 GFLOPS TDP: 195W Release Price: $499 20

21 Maxwell Architecture 21 GeForce GTX 750 Ti (Feb. 18, 2014) GM107, 28 nm process 1.87 billion transistors on a 148 mm 2 die CUDA Cores: 640 (5 SMs X 128 Cores) Memory Bandwidth: 86.4 GB/S Peak Performance: 1306 GFLOPS TDP: 60W Release Price: $149

22 CUDA Teaching Lab 22 GTX 750 (GM107) Compute Capability: CUDA Cores 1GB, 128-bit GDDR5 80 GB/S 1044 GFLOPS TDP: 55W RMB 799 GT 630 (GK208) Compute Capability: CUDA Cores 2GB, 64-bit GDDR GB/S GFLOPS TDP: 25W RMB 419

23 CUDA Installation 23 https://developer.nvidia.com/cuda-downloads

24 CUDA: deviceQuery 24

25 CUDA: bandwidthTest 25

26 CUDA Applications 26

27 CUDA Showcase 27

28 Heterogeneous Computing 28

29 Heterogeneous Computing 29

30 Grids, Blocks and Threads 30 Host Kernel 1 Kernel 2 Device Grid 1 Block (0, 0) Block (1, 0) Block (2, 0) Block (0, 1) Block (1, 1) Block (2, 1) Grid 2 Block (1, 1) Thread (0, 1) Thread (1, 1) Thread (2, 1) Thread (3, 1) Thread (4, 1) Thread (0, 2) Thread (1, 2) Thread (2, 2) Thread (3, 2) Thread (4, 2) Thread (0, 0) Thread (1, 0) Thread (2, 0) Thread (3, 0) Thread (4, 0)

31 Thread Block Threads have thread ID numbers within block. Threads use thread ID to select work. Threads are assigned to SMs in block granularity. Each GT200 SM can have maximum 8 blocks. Each GT200 SM can have maximum 1024 threads. Threads in the same block can share data and synchronize. Threads in different blocks cannot cooperate. Each block can execute in any order relative to other blocks. 31 Thread Id #: … m Thread program

32 Code Example 32

33 Transparent Scalability 33 Device Block 0Block 1 Block 2Block 3 Block 4Block 5 Block 6Block 7 Kernel grid Block 0Block 1 Block 2Block 3 Block 4Block 5 Block 6Block 7 Device Block 0Block 1Block 2Block 3Block 4Block 5Block 6Block 7

34 Memory Space 34 Grid Global Memory Block (0, 0) Shared Memory Thread (0, 0) Registers Thread (1, 0) Registers Block (1, 0) Shared Memory Thread (0, 0) Registers Thread (1, 0) Registers Host Constant Memory Each thread can: –Read/write per-thread registers –Read/write per-block shared memory –Read/write per-grid global memory –Read/only per-grid constant memory GeForce GTX 680 Memory Bandwidth … 192 GB/S Single-Precision Floating Point … 4B Peak Performance … 3090 GFLOPS Practical Performance … 48 GFLOPS

35 Hello World! 35 int main(void) { printf(“Hello World!\n”); return 0; } __global__ void mykernel(void) { } int main(void) { mykernel >>(); printf(“Hello World!\n”); return 0; }

36 Device Code CUDA keyword __global__ indicates a kernel function that: –Runs on the device. –Called from the host. CUDA keyword __device__ indicates a device function that: –Runs on the device. –Called from a kernel function or another device function. Triple angle brackets >> indicate a call from host code to device code. –Kernel launch nvcc separates source code into two components: –Device functions are processed by NVIDIA compiler. –Host functions are processed by standard host compiler. –$ nvcc hello.cu 36

37 Addition on Device 37 __global__ void add (int *a, int *b, int *c) { *c=*a+*b; } add () will execute on the device. add () will be called from the host. a, b, c must point to device memory. We need to allocate memory on GPU.

38 Memory Management Host and device memories are separate entities. Device pointers point to GPU memory. –May be passed to/from host code. –May not be dereferenced in host code. Host pointers point to CPU memory –May be passed to/from device code. –May not be dereferenced in device code. CUDA APIs for handling device memory –cudaMalloc(), cudaFree(), cudaMemcpy() – C equivalents : malloc(), free(), memcpy() 38

39 Addition on Device: main() 39 int main(void) { int a, b, c;// host copies int *d_a, *d_b, *d_c;// device copies int size=sizeof(int); // Allocate space for device copies of a, b, c cudaMalloc((void **)&d_a, size); cudaMalloc((void **)&d_b, size); cudaMalloc((void **)&d_c, size); a=2; b=7; // Copy inputs to device cudaMemcpy(d_a, &a, size, cudaMemcpyHostToDevice); cudaMemcpy(d_b, &b, size, cudaMemcpyHostToDevice);

40 Addition on Device: main() 40 // Launch add() kernel on GPU add >>(d_a,d_b,d_c); // Copy result back to host cudaMemcpy(&c, d_c, size, cudaMemcpyDeviceToHost); // Cleanup cudaFree(d_a); cudaFree(d_b); cudaFree(d_c); return 0; }

41 Moving to Parallel Each call to add() adds two integers. With add() running in parallel, we can do vector addition in parallel. add >>(d_a, d_b, d_c) Each parallel invocation of add() is referred to as a block. By using blockIdx.x to index into the array, each block handles a different index. Block can be 2D: –dim3 nblocks(M, N) –blockIdx.x, blockIdx.y 41

42 Vector Addition on Device 42 __global__ void add (int *a, int *b, int *c) { c[blockIdx.x]=a[blockIdx.x]+b[blockIdx.x]; } c[0]=a[0]+b[0]; Block 0 c[1]=a[1]+b[1]; Block 1 c[2]=a[2]+b[2]; Block 2 c[3]=a[3]+b[3]; Block 3

43 Vector Addition on Device: main() 43 # define N 512 int main(void) { int *a, *b, *c;// host copies int *d_a, *d_b, *d_c;// device copies int size=N*sizeof(int); // Allocate space for device copies of a, b, c cudaMalloc((void **)&d_a, size); cudaMalloc((void **)&d_b, size); cudaMalloc((void **)&d_c, size); // Allocate space of host copies of a, b, c // Set up initial values a=(int *)malloc(size); rand_ints(a, N); b=(int *)malloc(size); rand_ints(b, N); c=(int *)malloc(size); rand_ints(c, N);

44 Vector Addition on Device: main() 44 // Copy inputs to device cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice); cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice); // Launch add() kernel on GPU with N blocks add >(d_a, d_b, d_c); // Copy results back to host cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost); // Cleanup free(a); free(b); free(c); cudaFree(d_a); cudaFree(d_b); cudaFree(d_c); return 0; }

45 CUDA Threads Each block can be split into parallel threads. Threads can be up to 3D: –dim3 nthreads(M, N, P) –threadIdx.x, threadIdx.y, threadIdx.z 45 __global__ void add (int *a, int *b, int *c) { c[threadIdx.x]=a[threadIdx.x]+b[threadIdx.x]; } add >>(d_a, d_b, d_c);

46 Combining Blocks and Threads We have seen parallel vector addition using: –Many blocks with one thread each –One block with many threads Let’s adapt vector addition to use both blocks and threads. –Why bother? 46

47 Indexing 47 M=8; // 8 threads/block int index=threadIdx.x+blockIdx.x*M; int index=threadIdx.x+blockIdx.x*blockDim.x; __global__ void add (int *a, int *b, int *c) { int index=threadIdx.x+blockIdx.x*blockDim.x; c[index]=a[index]+b[index]; }

48 Indexing 48 #define N (2048*2048) #define M 512 // THREADS_PER_BLOCK … add >>(d_a, d_b, d_c); __global__ void add (int *a, int *b, int *c, int n) { int index=threadIdx.x+blockIdx.x*blockDim.x; if (index>(d_a, d_b, d_c, N);

49 Data Access Pattern 49 radius input output How many times?

50 Sharing Data Between Threads Each thread generates one output element. –blockDim.x elements per block Each input element needs to be read several times. –High I/O cost Within a block, threads can share data via shared memory. –Data are not visible to threads in other blocks. Extremely fast on-chip memory Declared using keyword: __shared__, allocated per block. Read ( blockDim.x+2*radius) input elements from global to shared memory. 50

51 Collaborative Threads input shared blockDim.x output elements Thread 0 produces the values of temp[i], i=0, 3, 13. Thread 9 requires the values of temp[i], i=9, 10, 11, 12, 13, 14, 15. void _syncthreads() T0

52 Kernel Synchronization 52 __global__ void vector_sum(int *in, int *out) { __shared__ int temp[BLOCK_SIZE+2*RADIUS]; int gindex=threadIdx.x+blockIdx.x*blockDim.x; // global index int lindex=threadIdx.x+RADIUS; // local index // Read input elements into shared memory temp[lindex]=in[gindex]; if (threadIdx.x { "@context": "http://schema.org", "@type": "ImageObject", "contentUrl": "http://images.slideplayer.com/13/3812684/slides/slide_51.jpg", "name": "Kernel Synchronization 52 __global__ void vector_sum(int *in, int *out) { __shared__ int temp[BLOCK_SIZE+2*RADIUS]; int gindex=threadIdx.x+blockIdx.x*blockDim.x; // global index int lindex=threadIdx.x+RADIUS; // local index // Read input elements into shared memory temp[lindex]=in[gindex]; if (threadIdx.x

53 void MatrixMulOnHost(float* M, float* N, float* P, int Width)‏ { int i, j, k; float a, b, sum; for (i = 0; i < Width; ++i)‏ for (j = 0; j < Width; ++j) { sum = 0; for (k = 0; k < Width; ++k) { a = M[i * width + k]; b = N[k * width + j]; sum += a * b; } P[i * Width + j] = sum; } 53 N PM Matrix Multiplication WIDTH i k k j

54 Single Thread Block 54 dim3 dimGrid(1,1); dim3 dimBlock(Width, Width); … MatrixMulKernel >>(Md, Nd, Pd, Width); … __global__ void MatrixMulKernel(float* Md, float* Nd, float* Pd, int Width)‏{ int k=0; float Pvalue = 0, Melement, Nelement; for (k = 0; k < Width; ++k)‏ { Melement = Md[threadIdx.y*Width+k]; // Md[threadIdx.y, k] Nelement = Nd[k*Width+threadIdx.x]; // Nd[k, threadIdx.x] Pvalue += Melement * Nelement; } // Pd[threadIdx.y, threadIdx.x] Pd[threadIdx.y*Width+threadIdx.x] = Pvalue; }

55 Single Thread Block What is the maximum size of the matrix? –Each thread computes one element of Pd. Each thread: –Loads a row of matrix Md. –Loads a column of matrix Nd. –Perform one multiply and addition for each pair of Md and Nd elements. CGMA –Compute to Global Memory Access 55 Grid 1 Block 1 48 Thread (2, 2)‏ WIDTH Md Pd Nd

56 Multiple Blocks 56 Md Nd Pd Pd sub TILE_WIDTH WIDTH bx 01 TILE_WIDTH TILE_WIDTH WIDTH Break Pd into square tiles. Each block calculates one tile: –Each threads calculates one element. –Block size equals to tile size. Require both block ID and thread ID.

57 Multiple Blocks: An Example 57 P 1,0 P 0,0 P 0,1 P 2,0 P 3,0 P 1,1 P 0,2 P 2,2 P 3,2 P 1,2 P 3,1 P 2,1 P 0,3 P 2,3 P 3,3 P 1,3 Block(0,0)Block(1,0) Block(1,1)Block(0,1) TILE_WIDTH = 2 Pd 1,0 Md 2,0 Md 1,1 Md 1,0 Md 0,0 Md 0,1 Md 3,0 Md 2,1 Pd 0,0 Md 3,1 Pd 0,1 Pd 2,0 Pd 3,0 Nd 0,3 Nd 1,3 Nd 1,2 Nd 1,1 Nd 1,0 Nd 0,0 Nd 0,1 Nd 0,2 Pd 1,1 Pd 0,2 Pd 2,2 Pd 3,2 Pd 1,2 Pd 3,1 Pd 2,1 Pd 0,3 Pd 2,3 Pd 3,3 Pd 1,3

58 Multiple Blocks: Indexing TILE_WIDTH Block: blockIdx.x, blockIdx.y Thread:threadIdx.x, threadIdx.y Row: blockIdx.y * TILE_WIDTH + threadIdx.y Col:blockIdx.x * TILE_WIDTH + threadIdx.x 58 (0,0)(1,0)(2,0)(3,0) (0,1)(1,1)(2,1)(3,1) (0,2)(1,2)(2,2)(3,2) (0,3)(1,3)(2,3)(3,3) blockIdx.y blockIdx.xthreadIdx.x threadIdx.y

59 Multiple Blocks: Device Code 59 __global__ void MatrixMulKernel(float* Md, float* Nd, float* Pd, int Width)‏{ // Calculate the row index of the Pd element and Md int Row=blockIdx.y*TILE_WIDTH+threadIdx.y; // Calculate the col index of the Pd element and Nd int Col=blockIdx.x*TILE_WIDTH+threadIdx.x; int k; float Pvalue = 0; // Each thread computes one element of sub-matrix for (k = 0; k < Width; ++k)‏ Pvalue += Md[Row*Width+k] * Nd[k*Width+Col]; Pd[Row*Width+Col] = Pvalue; }

60 Block Granularity Each SM in GT200 can take up to 1024 threads and 8 blocks. 8 × 8: 64 threads per block, 1024/64=12 blocks, 64 × 8=512 threads per SM 16 × 16: 256 threads per block, 1024/256=4 blocks, full capacity! 32 × 32: 1024 threads per block, exceeding the limit of 512 threads/block 60 t0 t1 t2 … tm Blocks SP Shared Memory MT IU SP Shared Memory MT IU t0 t1 t2 … tm SM 1SM 0 Blocks

61 Global Memory Access 61 T 1,0 T 0,0 T 0,1 T 1,1 2 × 2 Thread Block Md Nd Each thread requires one row from Md and one column from Nd. For a k × k thread block, each row/column will be accessed k times. To reduce the global memory I/O, it is beneficial to load the required data once into the shared memory.

62 Splitting Md 62 Md 0,0 Md 1,0 Md 2,0 Md 3,0 Md 0,1 Md 1,1 Md 2,1 Md 3,1 Mds 0,0 Mds 1,0 Mds 0,1 Mds 1,1 Mds 0,0 Mds 1,0 Mds 0,1 Mds 1,1 Md Mds Phase 1 Phase 2 shared The shared memory per SM is limited (e.g., 64KB). Shared among all blocks in the same SM. Luckily, not all data needs to be in the shared memory simultaneously.

63 Shared Memory: Device Code 63 __global__ void MatrixMulKernel(float* Md, float* Nd, float* Pd, int Width) { 1. __shared__ float Mds[TILE_WIDTH][TILE_WIDTH]; 2. __shared__ float Nds[TILE_WIDTH][TILE_WIDTH]; 3. int bx = blockIdx.x; int by = blockIdx.y; 4. int tx = threadIdx.x; int ty = threadIdx.y; // Identify the row and column of the Pd element to work on 5. int Row = by * TILE_WIDTH + ty; 6. int Col = bx * TILE_WIDTH + tx; 7. float Pvalue = 0; // Loop over the Md and Nd tiles required to compute the Pd element 8.for (int m = 0; m < Width/TILE_WIDTH; ++m) { // Collaboratively load Md and Nd tiles into shared memory 9. Mds[ty][tx] = Md[Row*Width + (m*TILE_WIDTH + tx)]; 10. Nds[ty][tx] = Nd[Col + (m*TILE_WIDTH + ty)*Width]; 11. __syncthreads(); // Make sure the shared memory is ready

64 Shared Memory: Device Code for (int k = 0; k < TILE_WIDTH; ++k) 13. Pvalue += Mds[ty][k] * Nds[k][tx]; // Make sure all threads have finished working on the shared memory 14. __syncthreads(); } 15. Pd[Row*Width+Col] = Pvalue; } Each SM in G80 can take up to 768 threads and 8 blocks. Each SM has 16KB shared memory. For a tile of size 16 × 16, each block requires 16 × 16 × 4 = 1KB for Mds. Totally, 2KB are required for each block and 8 blocks can be supported. However, since 768/(16 × 16) = 3, only 3 blocks and 6KB will be in use.

65 Performance Considerations GPU computing is easy: –Host, Device, Kernel, Block, Thread –GPU Cards –Up and running in a few days As long as performance is not a major concern: –Various performance bottlenecks –10 × speedup is often within your reach. –100 × speedup takes significant amount of tuning efforts. 65

66 Thread Execution Conceptually, threads in a block can execute in any order with respect to each other. –Exception: barrier synchronizations Each thread block is partitioned into warps. –Hardware cost considerations –The unit of thread scheduling in SMs –32 threads per warp: [0,…, 31], [32,…, 63] … All threads in a warp execute the same instruction. SM hardware implements zero-overhead thread scheduling. –Can tolerate long-latency operations with several warps around. –GPU does not require as much chip area for cache memories and branch prediction mechanisms as CPUs. 66

67 Warp Scheduling 67 Suppose 1 global memory access is needed for every 4 instructions. Instruction: 4 clock cycles Memory latency: 200 clock cycles At least 14 warps are required to keep the units fully utilized. A B C D A

68 Flow Divergence 68 warp 8 instruction 11 SM multithreaded Warp scheduler warp 1 instruction 42 warp 3 instruction 95 warp 8 instruction time warp 3 instruction 96 SIMT can reduce the cost of fetching and processing instructions. SIMT works well when all threads in a warp follow the same control flow. Multiple sequential passes may be required for an if-then-else construct. if X X Y Y thenelse

69 Flow Divergence 69

70 70

71 Flow Divergence Main performance concern with branching is divergence. –Threads within a thread take different paths. –The control paths are traversed one at a time. How to avoid divergence when the branch condition is a function of thread ID? –With divergence: if (threadIdx.x>2) { } Threads 0, 1, and 2 follow a different path than the rest threads in the warp. –Without divergence: if (threadIdx.x/WARP_SIZE>=2) { } Creates two different paths for threads in a block. Branch granularity is a whole multiple of warp size. All threads in any given warp follow the same path. 71

72 Memory Coalescing Dynamic Random Access Memory (DRAM) –Each bit is stored in a separate capacitor. –All storage locations have nearly identical access time. –In practice, many consecutive locations are accessed in parallel. –All threads in a warp should access continuous memory locations (coalescing) to maximize memory bandwidth utilization. 72 Md Nd WIDTH Thread 1 Thread 2 Not coalescedCoalesced WIDTH

73 Memory Layout of a Matrix in C 73 M 2,0 M 1,1 M 1,0 M 0,0 M 0,1 M 3,0 M 2,1 M 3,1 M 2,0 M 1,0 M 0,0 M 3,0 M 1,1 M 0,1 M 2,1 M 3,1 M 1,2 M 0,2 M 2,2 M 3,2 M 1,2 M 0,2 M 2,2 M 3,2 M 1,3 M 0,3 M 2,3 M 3,3 M 1,3 M 0,3 M 2,3 M 3,3 M T0T0 T1T1 T2T2 T3T3 Time Period 1 T0T0 T1T1 T2T2 T3T3 Time Period 2 Time

74 Memory Layout of a Matrix in C 74 M 2,0 M 1,0 M 0,0 M 3,0 M 1,1 M 0,1 M 2,1 M 3,1 M 1,2 M 0,2 M 2,2 M 3,2 M 1,3 M 0,3 M 2,3 M 3,3 T0T0 T1T1 T2T2 T3T3 Time Period 1 T0T0 T1T1 T2T2 T3T3 Time Period 2 Time M M 2,0 M 1,1 M 1,0 M 0,0 M 0,1 M 3,0 M 2,1 M 3,1 M 1,2 M 0,2 M 2,2 M 3,2 M 1,3 M 0,3 M 2,3 M 3,3

75 Shared Memory Architecture Many threads access memory: –Shared memory is divided in banks. –Successive 32-bit words are assigned to successive banks. –Each bank has a bandwidth of 32 bits per clock cycle. –G80 has 16 banks: bank=address % 16 –Same as the size of half a warp Each memory bank can service one address per cycle. –Can service as many simultaneous accesses as the number of banks. Multiple simultaneous accesses to the same bank may result in a bank conflict. –Conflicting accesses are serialized. –No bank conflicts between different half warps. 75

76 Bank Conflicts Shared memory is as fast as registers if there are no bank conflicts. The fast case: –If all threads of a half-warp access different banks, there is no bank conflict. –If all threads of a half-warp access the identical address, there is no bank conflict (broadcast). The slow case: –Bank Conflict: Multiple threads in the same half-warp access the same bank. –Must serialize the accesses. –Cost = max # of simultaneous accesses to a single bank 76 Bank 15 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 Bank 0

77 Bank Addressing Example 77 No Bank Conflicts –Linear addressing No Bank Conflicts –Random 1:1 Permutation Bank 15 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 Bank 0 Thread 15 Thread 7 Thread 6 Thread 5 Thread 4 Thread 3 Thread 2 Thread 1 Thread 0 Bank 15 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 Bank 0 Thread 15 Thread 7 Thread 6 Thread 5 Thread 4 Thread 3 Thread 2 Thread 1 Thread 0

78 Bank Addressing Example 78 2-way Bank Conflicts –Linear addressing stride = 2 8-way Bank Conflicts –Linear addressing stride = 8 Thread 11 Thread 10 Thread 9 Thread 8 Thread 4 Thread 3 Thread 2 Thread 1 Thread 0 Bank 15 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 Bank 0 Thread 15 Thread 7 Thread 6 Thread 5 Thread 4 Thread 3 Thread 2 Thread 1 Thread 0 Bank 9 Bank 8 Bank 15 Bank 7 Bank 2 Bank 1 Bank 0 x8

79 Partitioning of SM Resources Execution resources in SM –Registers –Block Slots (GT200: 8) –Thread Slots (GT200: 1024) –Number of 16 × 16 blocks = 1024/(16 × 16) = 4 –Determine the number of threads running on a SM. –Subtle interactions that may cause underutilization of resources Register File –Store automatic variables declared in a CUDA kernel. –G80: 32KB (8192 entries) for each SM –Dynamically partitioned across all blocks in the same SM. –Each thread can only access registers assigned to itself. 79

80 SM Resources Example For 16 × 16 blocks, if each thread uses 10 registers: –Each block requires 16 × 16 × 10 = 2560 registers. –Number of blocks = 8129/2560 = 3 If each thread increases the use of registers by 1: –Each block now requires 16 × 16 × 11 = 2816 registers. –Number of blocks = 8129/2816 = 2 –Only two blocks can run on a SM. –Number of threads drops from 768 to 512 –1/3 reduction of parallelism due to the single extra automatic variable! 80

81 Occupancy Calculator 81

82 Instruction Mix Each processor core has limited instruction processing bandwidth. Every instruction consumes processing bandwidth: –Floating point calculation –Load instruction –Branch instruction We should try to increase the efficiency of instructions. 82 for (int k=0; k { "@context": "http://schema.org", "@type": "ImageObject", "contentUrl": "http://images.slideplayer.com/13/3812684/slides/slide_81.jpg", "name": "Instruction Mix Each processor core has limited instruction processing bandwidth.", "description": "Every instruction consumes processing bandwidth: –Floating point calculation –Load instruction –Branch instruction We should try to increase the efficiency of instructions. 82 for (int k=0; k

83 Instruction Mix 83 Pvalue+=Mds[ty][0]*Nds[0][tx]+… +Mds[ty][15]*Nds[15][tx]; Loop Unrolling Express the dot-product computation as one long multiply-add expression. Eliminate the loop branch instruction. Eliminate the loop counter update. Matrix indices are constants rather than a variable. With the help of compiler, address arithmetic instructions can be also eliminated!

84 Dynamic Parallelism A child CUDA kernel can be called from within a parent CUDA kernel, without CPU involvement. Extension to flat, single-level of parallelism Requires Compute Capability 3.5+ Benefits: –Simplified CPU/GPU Cooperation –Dynamic Load Balancing –Data-Dependent Execution –Recursive Parallel Algorithms 84 CPU GPU CPU GPU

85 What does it mean? 85

86 What does it mean? 86

87 Example __global__ ChildKernel(void* data){ //Operate on data } __global__ ParentKernel(void *data){ ChildKernel >>(data); } // In Host Code ParentKernel >(data); 87 __global__ RecursiveKernel(void*data){ if(continueRecursion == true) RecursiveKernel >>(data); }

88 Matrix Example for (int i=0; i { "@context": "http://schema.org", "@type": "ImageObject", "contentUrl": "http://images.slideplayer.com/13/3812684/slides/slide_87.jpg", "name": "Matrix Example for (int i=0; i

89 Matrix Example 89 for (int i=0; i { "@context": "http://schema.org", "@type": "ImageObject", "contentUrl": "http://images.slideplayer.com/13/3812684/slides/slide_88.jpg", "name": "Matrix Example 89 for (int i=0; i

90 Matrix Example __global__ void con_kernel(int i){ convolution_function(i, threadIdx.x); } __global__ void dynamic_parallelism_kernel(int *M){ con_kernel >>(blockIdx.x); } //In Host Code dynamic_parallelism_kernel >>(M); 90

91 Synchronization __global__ void Parent_Kernel() {... //Kernel code if(threadIdx.x==0){ Child_Kernel >>(); // Thread will launch kernel and keep going cudaDeviceSynchronize(); // Make thread wait for Child_Kernel to complete } __syncthreads(); //If all threads in the block need Child_Kernel to complete... //Code that needs data generated by Child_Kernel } 91

92 Timing GPU Kernels 92 float time; cudaEvent_t start, stop; cudaEventCreate(&start); cudaEventCreate(&stop); cudaEventRecord(start, 0); // Place the start event kernel >>(..); // Returns immediately cudaEventRecord(stop, 0); // Place the stop event cudaEventSynchronize(stop); // Make sure stop is reached cudaEventElapsedTime(&time, start, stop); cudaEventDestroy(start); cudaEventDestroy(stop); stopKernelstart Stream 0

93 Multiple Kernels 93 // Create two streams cudaStream_t stream[2]; for (int i=0; i<2; ++i) cudaStreamCreate(&stream[i]); // Launch a Kernel from each stream KernelOne >>(..); KernelTwo >>(..); // Destroy the streams for (int i=0; i<2; ++i) cudaStreamDestroy(stream[i]); Synchronization is implied for events within the same stream. More than one stream can be associated with a GPU.

94 Multiple GPUs 94 int nDevices; cudaGetDeviceCount(&nDevices); cudaDeviceProp prop; for (int i=0; i { "@context": "http://schema.org", "@type": "ImageObject", "contentUrl": "http://images.slideplayer.com/13/3812684/slides/slide_93.jpg", "name": "Multiple GPUs 94 int nDevices; cudaGetDeviceCount(&nDevices); cudaDeviceProp prop; for (int i=0; i

95 Streams and Multiple GPUs Streams belong to the GPU that was active when they were created. Calls to a stream are invalid if the associated GPU is not active. 95 cudaSetDevice(0); cudaStreamCreate(&streamA); cudaSetDevice(1); cudaStreamCreate(&streamB); // Launch kernels KernelOne >>(..); // Invalid! KernelTwo >>(..); // Valid

96 Floating Point Considerations Numeric values are represented as bit patterns. IEEE Floating Point Standard –Sign (S), Exponent (E) and Mantissa (M) –Each (S, E, M) pattern uniquely identifies a floating point number. For each bit pattern, it numeric value is derived as: –Value = (-1) S × M × {2 E }, where 1.0 B ≤ M < 10.0 B The interpretation of S: –S=0: Positive Number –S=1: Negative Number 96

97 Normalized Representation of M Subscripts D and B are for decimal place and binary place values respectively. Specifying 1.0 B ≤ M < 10.0 B makes the mantissa value for each floating point number unique. –For example: 0.5 D = 1.0 B × 2 -1 –The only valid mantissa value is M=1.0 B. –Neither 10.0 B × 2 -2 (M = 10.0 B ) nor 0.1 B × 2 0 (M = 0.1 B ) qualifies. –Just like 10.0 D × 10 5, or 0.9 D × are not valid. Because all mantissa values are of the form 1.XX…, we can omit the “1.” part from the representation. –The mantissa value of 0.5 D in a 2-bit mantissa is 00, by omitting “1.” from –With the IEEE format, an n-bit mantissa is effectively an (n+1)-bit mantissa. 97

98 Excess Encoding of E 98 Decimal ValueTwo’s ComplementExcess-3 Reserved In an n-bit exponent representation, 2 n-1 -1 is added to its two's complement to form its excess representation. Monotonically (-1) S × 1.M × 2 (E-2^(n-1)+1)

99 Representable Numbers 99 No-zeroAbrupt UnderflowDenormalization E MS=0S=1S=0S=1S=0S= (2 -1 ) *2 -3 -( *2 -3 )001* * *2 -3 -( *2 -3 )002* * *2 -3 -( *2 -3 )003* * (2 0 ) *2 -2 -(2 0 +1*2 -2 )2 0 +1*2 -2 -(2 0 +1*2 -2 )2 0 +1*2 -2 -(2 0 +1*2 -2 ) *2 -2 -(2 0 +2*2 -2 )2 0 +2*2 -2 -(2 0 +2*2 -2 )2 0 +2*2 -2 -(2 0 +2*2 -2 ) *2 -2 -(2 0 +3*2 -2 )2 0 +3*2 -2 -(2 0 +3*2 -2 )2 0 +3*2 -2 -(2 0 +3*2 -2 ) (2 1 ) *2 -1 -(2 1 +1*2 -1 )2 1 +1*2 -1 -(2 1 +1*2 -1 )2 1 +1*2 -1 -(2 1 +1*2 -1 ) *2 -1 -(2 1 +2*2 -1 )2 1 +2*2 -1 -(2 1 +2*2 -1 )2 1 +2*2 -1 -(2 1 +2*2 -1 ) *2 -1 -(2 1 +3*2 -1 )2 1 +3*2 -1 -(2 1 +3*2 -1 )2 1 +3*2 -1 -(2 1 +3*2 -1 ) 11 Reserved Pattern

100 Representable Numbers The exponent bits define the major intervals of representable numbers. The mantissa bits define the number of representable numbers in each interval. Zero is not representable in this format. Representable numbers become closer to each other toward 0. There is a gap in representable numbers in the vicinity of

101 Representing Zero Abrupt Underflow –Treats all bit patters with E=0 as 0. –Takes away several representable numbers near zero and lumps them all into Denormalization –Relaxes the normalization requirement for numbers very close to 0. –Whenever E=0, the mantissa is assumed to be 0.xx. –The exponent is assumed to be the same as the previous interval. 0.M × 2 -2^(n-1) (S E M)  0.01 X 2 0 = 2 -2

102 Accuracy and Rounding 1.00 × × 2 1 =0.001 × × 2 1 = × 2 1 ≈ 1.00 × 2 1 (Error = × 2 1 ) 1.00 × × × × 2 -2 =1.00 × × × 2 -2 =1.00 × × 2 -2 =1.00 × 2 1 [1.00 × × 2 0 ]+ [1.00 × × 2 -2 ] =1.00 × × 2 -1 =1.01 × 2 1 Sorting data in ascending order may help achieve greater accuracy. –Numbers with similar numerical values are close to each other. 102

103 Single vs. Double Precision GPUs were traditionally not good at double precision calculation. –Requires compute capability 1.3 or above. –Around 1/8 of single precision performance. –Improved greatly to 1/2 with Fermi architecture. Important to avoid using double precision when it is not necessary. –Add ‘ f ’ specifier on float literals: Y=X*0.123; // double assumed Y=X*0.123f; // float explicit –Use float version of standard library functions: Y=sin(X); // double assumed Y=sinf(X); // single precision explicit 103

104 Matlab in Parallel Matlab: Numerical Computing Environment Parallel Computing Toolbox (PCT) Offload work from one MATLAB session (client) to other MATLAB sessions (workers). Run as many as eight MATLAB workers (2011b) on your local machine in addition to your MATLAB client session. 104

105 Parfor 105 Parallel for -loop The parfor body is executed on the client and workers. The data on which parfor operates is sent from the client to workers, and the results are sent back to the client and pieced together. MATLAB workers evaluate iterations in no particular order, and independently of each other. Classification of Variables –Loop, Sliced, Reduction, Broadcast, Temporary

106 Classification of Variables 106 a=0; c=pi; z=0; r=rand(1,10); parfor i=1:10 a=i; z=z+i; b(i)=r(i); if i<=c d=2*a; end temporaryloop reduction broadcast sliced

107 Parfor Example 107 X=zeros(1,N); for i = 1:N x(i)=sin(i/N*2*pi); end X=zeros(1,N); matlabpool open local 8 % create 8 workers parfor i = 1:N X(i)=sin(i/N*2*pi); end matlabpool close % close all workers parallelization

108 Notes on Parfor Each loop must be independent of other loops. In the Windows Task Manager, there are multiple Matlab processes: –Higher CPU Usage –Higher Memory Usage It incurs significant overhead: only works with long loop iterations and/or time consuming calculations. Be prepared to be surprised: –Some Matlab functions are already optimized for multithreading. –The practical speedup value is generally quite moderate. 108

109 GPU Accelerated Matlab Matlab users can now easily enjoy the benefits of GPU computing. Capabilities –Evaluating built-in functions on the GPU. –Running MATLAB code on the GPU. Requirements –Matlab 2014a (Recommended) –NVIDIA CUDA-enabled devices with compute capability of 1.3 or greater –NVIDIA CUDA device driver 3.1 or greater Check the GPU environment –gpuDeviceCount: number of available GPU devices –gpuDevice: select and query GPU device 109

110 Create Data on GPU Transferring data between workspace and GPU: Directly creating GPU data: 110 M = rand(6); G = gpuArray(single(M)); N = gather(G); Workspace GPU G = ones(100,100,50, 'single', 'gpuArray'); size(G) classUnderlying(G) single

111 Execute Code on GPU Run Built-In Functions Run Element-Wise Matlab Code 111 X = rand(1000,'single','gpuArray'); Gfft = fft(X); Y = gather(Gfft); function c = myCal(rawdata, gain, offst) c = (rawdata.* gain) + offst; meas = ones(1000)*3; // CPU gn = rand(1000,'gpuArray')/100; // GPU offs = rand(1000,'gpuArray')/50; // GPU corrected = results = gather(corrected);

112 Timing GPU Code 112 A = rand(1024,'gpuArray'); fh gputimeit(fh); gd = gpuDevice(); tic(); B = fft(A); wait(gd); t = toc(); A = rand(12000,400,'gpuArray'); B = rand(400,12000,'gpuArray'); f t = gputimeit(f); X = rand(1000,'gpuArray'); f t1 = gputimeit(f,1); t3 = gputimeit(f,3) ;

113 Testing Host-GPU Bandwidth 113 sizeOfDouble = 8; sizes = power(2, 14:28); sendTimes = inf(size(sizes)); gatherTimes = inf(size(sizes)); for i=1:numel(sizes) numElements = sizes(i)/sizeOfDouble; hostData = randi([0 9], numElements, 1); gpuData = gpuArray.randi([0 9], numElements, 1); sendFcn sendTimes(i) = gputimeit(sendFcn); gatherFcn gatherTimes(i) = gputimeit(gatherFcn); end sendBandwidth = (sizes./sendTimes)/1e9; [maxSendBandwidth, maxSendIdx] = max(sendBandwidth); gatherBandwidth = (sizes./gatherTimes)/1e9; [maxGatherBandwidth, maxGatherIdx] = max(gatherBandwidth);

114 Testing Host-GPU Bandwidth 114

115 Testing CPU Bandwidth 115 sizeOfDouble = 8; sizes = power(2, 14:28); memoryTimesHost = inf(size(sizes)); for i=1:numel(sizes) numElements = sizes(i)/sizeOfDouble; hostData = randi([0 9], numElements, 1); plusFcn 1.0); memoryTimesHost(i) = timeit(plusFcn); end memoryBandwidthHost = 2*(sizes./memoryTimesHost)/1e9; [maxBWHost, maxBWIdxHost] = max(memoryBandwidthHost);

116 Testing GPU Bandwidth 116 memoryTimesGPU = inf(size(sizes)); for i=1:numel(sizes) numElements = sizes(i)/sizeOfDouble; gpuData = gpuArray.randi([0 9], numElements, 1); plusFcn 1.0); memoryTimesGPU(i) = gputimeit(plusFcn); end memoryBandwidthGPU = 2*(sizes./memoryTimesGPU)/1e9; [maxBWGPU, maxBWIdxGPU] = max(memoryBandwidthGPU);

117 Bandwidth: CPU vs. GPU 117

118 Testing Matrix Multiplication 118 sizes = power(2, 12:2:24); N = sqrt(sizes); mmTimesHost = inf(size(sizes)); mmTimesGPU = inf(size(sizes)); for i=1:numel(sizes) A = rand(N(i), N(i)); B = rand(N(i), N(i)); mmTimesHost(i) = A = gpuArray(A); B = gpuArray(B); mmTimesGPU(i) = end mmGFlopsHost = (2*N.^3 - N.^2)./mmTimesHost/1e9; [maxGFlopsHost,maxGFlopsHostIdx] = max(mmGFlopsHost); mmGFlopsGPU = (2*N.^3 - N.^2)./mmTimesGPU/1e9; [maxGFlopsGPU,maxGFlopsGPUIdx] = max(mmGFlopsGPU);

119 Testing Matrix Multiplication 119

120 Testing Matrix Multiplication 120

121 Review What are the differences among MPI, OpenMP and CUDA? Why is GPU suitable for high performance computing? What is the general framework of CUDA programming? What is a kernel function and how to call it from the host code? What is the advantage of splitting a block into threads? Why do we need multiple thread blocks? What are the major memory types in CUDA? When should we use shared memory? What resource factors are critical to GPU programming? 121

122 Review What is a warp and why do we need it? What is flow divergence and how to avoid it? What is bank conflict? What is instruction mix? What are the benefits of Dynamic Parallelism? How to measure the performance of GPU code? How to run kernel functions in parallel? How is a floating point number represented in the IEEE format? How to execute Matlab code on GPU? 122


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