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LCWS12 Arlington October 22-26, 2012 D. Attié, P. Colas, M. Dixit, P. Hayman, T. Maerschalk, A. Robichaud, J. Timmermans, W. Wang.

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Presentation on theme: "LCWS12 Arlington October 22-26, 2012 D. Attié, P. Colas, M. Dixit, P. Hayman, T. Maerschalk, A. Robichaud, J. Timmermans, W. Wang."— Presentation transcript:

1 LCWS12 Arlington October 22-26, 2012 D. Attié, P. Colas, M. Dixit, P. Hayman, T. Maerschalk, A. Robichaud, J. Timmermans, W. Wang

2 24/10/2012P. Colas - Micromegas TPC - 6 modules2 38(*) member + 7 observer institutes from 12 countries (*) 25 signed the MOA

3 The EUDET (FP6) setup at DESY is operational since 2008 Upgraded within AIDA (FP7): autonomous magnet with 2 cryo-coolers since July 24/10/2012P. Colas - Micromegas TPC - 6 modules3 SiPM trigger Field cage

4 Resistive coating on top of an insulator: Continuous RC network which spreads the charge from  (avalanche)~15µ to mm: matching pad width improves position sensitivity 24/10/20124P. Colas - Micromegas TPC - 6 modules M. Dixit, A. Rankin, NIM A 566 (2006) 28 Z=20cm, 200 ns shaping PAD RESPONSE : Relative fraction of ‘charge’ seen by the pad, vs x(pad)- x(track) x(pad) – x(track) (mm)

5  New detector : new routing to adapt to new connectors, lower anode resistivity (3 M  /sq), new res. foil grounding on the edge of the PCB.  New 300 points flat connectors (zero extraction force)  New front end: keep naked AFTER chips and remove double diodes (count on resistive foil to protect against sparks)  New Front End Mezzanine (FEMI)  New back-end for up to 12 modules  New DAQ, 7-module and more compact format  New trigger discriminator and logic (FPGA). 24/10/2012P. Colas - Micromegas TPC - 6 modules5 D. Calvet et al., IEEE Real Time 2012

6 The multi-module configuration allows new studies : - Performance in cracks - Module misalignment - distortions 24/10/2012P. Colas - Micromegas TPC - 6 modules6

7 24/10/2012P. Colas - Micromegas TPC - 6 modules7 Smooth data taking in July, with over evts. Air cooling and temperature control. However 6 modules only, 2 of them prototype or pre-serie, imperfect contacts

8 24/10/2012P. Colas - Micromegas TPC - 6 modules8 Thanks to Bo Li, Keisuke Fujii, Gilles de Lentdecker, M. Killenberg,…

9 Effective gain vs mesh voltage is measured by using the fitted MPV of the (Landau) distribution of the measured charge. It compares well with direct gain measurements with a 55Fe source on a detector without resistive foil (x2 lower) 24/10/2012P. Colas - Micromegas TPC - 6 modules9

10 Study the hit reconstruction efficiency at or near the crack: take data with beam, moving by steps of 2mm Beam direction Outside crack In crack Upper crackLower crack Padrow number (3x24=72) Hits with ADC>150, 1-track evts 24/10/2012P. Colas - Micromegas TPC - 6 modules10

11 Number of hits vs x Effect of cracks is felt in an area ~1cm around. In the worst case, 50% of the hits are lost 24/10/2012P. Colas - Micromegas TPC - 6 modules11

12 24/10/2012P. Colas - Micromegas TPC - 6 modules12 ROW NUMBER : 3x24 = 72 Displacement in mm

13 24/10/2012P. Colas - Micromegas TPC - 6 modules13

14 24/10/2012P. Colas - Micromegas TPC - 6 modules14

15 Fitted displacement : Rotation :  = -1.7 mrad, 3.7 mrad and 8.4 mrad Translation:  x = -54 µm, 180 µm and 278 µm After alignment : only distortions remain (probably ExB effect) Maximum effect of distortions 400µm 24/10/2012P. Colas - Micromegas TPC - 6 modules15 Z=10cm

16 GdSP : gaseous detector signal processing (or Go digital as Soon as Possible) CERN-based collaboration lead by Paul Aspell, including Saclay: F. Guilloux and E. Delagnes, continuing S-ALTRO evolution. Common development for CMS GEM µ-chambers and LC TPC. Recently considering ALICE upgrade (GEM TPC and µ chambers). Main developments : 130 nm technology, 64 or 128 channels, low noise and ultra-low consumption, many power domains to ease power switching First Si test to be submitted in February 2013 (AIDA) Goals for the FE : for 10 pF detector capacitance and 100 ns peaking time ENC<900 e- and power < 1mW/ch 24/10/2012P. Colas - Micromegas TPC - 6 modules16

17 Parameter VFAT2 (IBM 0.25) SALTRO (IBM 0.13) VFAT3 / GdSP (IBM 0.13) Linear range +- 12fC150fCMax 200fC Input capacitance (pF) – 10 – 30 – 60 Noise ~500e-  40-60e- 25ns ~ 650e-  120ns < SAltro /VFAT From Paul Aspell ParameterVFAT2SALTROVFAT3 / GdSP Power (mW/channel) 1.5 (IBM 250nm) (incl. comparator) 10<< 1 Starting from data measured on ABCN (130nm design by Jan Kaplon for ATLAS SCT): * 800 5pF, tp=22ns, 100µW * assuming serie noise only + strong inversion for the input transistor  we can hope 530 tp= 100ns, 200µW  Ultra Low power low noise design seems feasible (cf slide 6) 2/10/2012

18  Groups involved Slow Control (SPI) Registers DAC CSA 2Calib.PZ 2 CSA 1/2PZ 1 CSA 1/2/3Calib.PZ 1/2 x6 x2 MUX 9  1 Sallen Key DDF MUX 3  1 BiasRegulator Shaper Output Buffer Bypass DDF CSA 2Calib.PZ 2DDF x8 CEA-IRFUINFN-BARI CERN

19 Summary Successful test of 6 modules at a time - Most integration questions addressed - Improvements needed in contacts of the flat connectors - Multi-modules aspects addressed: alignment, reconstruction Next step: 7 modules high quality test, full calibration on the test bench, detailed analysis in R&D projects: thinner meshes, other charge dispersion devices (ceramic with ruthenium oxide). Then a larger module with smaller pads for the inner wheel. 24/10/2012P. Colas - Micromegas TPC - 6 modules19 Thanks to our DESY colleagues, especially Ralf Diener, Christophe Rosemann and Felix Müller


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